Dynamic Bit Line Bias for Non-Volatile Memory Programming
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in accurately programming threshold voltage ranges, particularly as they are scaled down, leading to wide distributions and increased programming time, due to tradeoffs between programming speed and voltage overshoots, and variations in program noise among storage elements.
Innovation Solution
A programming technique that adjusts the bit line voltage based on the count of program pulses applied to each storage element, ensuring a uniformly slow programming speed between verify levels, optimizing programming for each element and achieving a tighter threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming speed is increased, then productivity is improved, but manufacturing precision deteriorates due to voltage overshoots and wide threshold voltage distributions
Solution Approach 1:
The patent applies dynamics by making the bit line voltage adjustable and time-dependent. Instead of using a fixed voltage level, the system dynamically changes the bit line voltage from an initial level to a final level during the programming process. This dynamic adjustment allows the programming speed to be modulated, enabling faster programming while maintaining tight threshold voltage distributions through controlled voltage transitions.
Solution Approach 2:
The patent implements parameter changes by varying the bit line voltage level during programming. The voltage is changed from an initial value to a final value based on the programming stage and storage element state. This parameter modification enables optimization of both programming speed and threshold voltage precision, resolving the contradiction between fast programming and narrow voltage distributions.
2Device complexity
If a fixed bit line voltage is used during programming, then device complexity is reduced, but manufacturing precision deteriorates due to variations in program noise among storage elements
Solution Approach 1:
The patent applies local quality by assigning different bit line voltage levels to different storage elements or groups of storage elements based on their individual programming needs. Instead of using a uniform voltage for all elements, the system provides localized voltage adjustment, ensuring that each storage element receives the appropriate voltage level to minimize program noise variations and achieve consistent threshold voltage programming.
3Ease of operation
If programming is performed without dynamic voltage adjustment, then ease of operation is improved, but productivity deteriorates due to increased programming time required to achieve accurate threshold voltage ranges
Solution Approach 1:
The patent implements periodic action by applying programming pulses in sequences with different bit line voltage levels. The system alternates between different voltage stages during programming, using periodic verification and adjustment cycles. This periodic approach enables accurate threshold voltage programming while maintaining reasonable programming speeds, balancing operational simplicity with productivity.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3D
AI summary
A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.