Dynamic Bit Line Precharging for Virtual Ground Memory Arrays
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Solution Overview
Problem
Virtual ground arrays of non-volatile memory cells face challenges in effective read and programming operations due to inconsistencies in terminal connections and voltage management.
Innovation Solution
A non-volatile memory device with bi-directional memory cells arranged in a virtual ground configuration, utilizing a specific terminal connection scheme and precharging methods to manage global and local bit lines, allowing for efficient reading and programming by controlling voltage differentials and capacitively coupling voltages to achieve programming of select memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If virtual ground arrays use traditional read and programming methods, then the basic memory operations can be performed, but the operations suffer from inefficiency and reliability issues due to terminal connection inconsistencies and voltage management problems
Solution Approach 1:
The patent implements dynamic terminal connections where the virtual ground terminal is selectively connected to different voltage potentials (ground or positive voltage) depending on the operation mode. The bit lines are dynamically switched between ground and precharged states, allowing the memory array to adapt its electrical characteristics for optimal read and programming operations, thereby improving both speed and reliability
Solution Approach 2:
The patent changes voltage parameters dynamically during operations. Bit lines are precharged to specific voltages before reads, and programming voltages are precisely controlled to achieve reliable cell programming. The virtual ground potential is changed between operations to enable different functional modes, optimizing performance for each operation type
2Manufacturing precision
If global bit lines are precharged to manage voltage differentials, then programming precision is improved, but the complexity of voltage management increases
Solution Approach 1:
The patent precharges global bit lines to specific voltages before programming operations to establish precise voltage differentials across selected memory cells. This preliminary voltage setup ensures accurate programming control. The system manages complexity by systematically precharging only the necessary bit lines involved in the current operation, rather than all bit lines
Solution Approach 2:
The patent divides the bit line system into global bit lines and local bit lines, with independent precharging control. This segmentation allows selective voltage management where only the global bit line associated with the selected word line and bit line pair needs precise precharging, reducing the overall management complexity while maintaining programming precision
3Adaptability or versatility
If alternating local bit lines are connected to different global bit lines, then array utilization is improved, but the difficulty of detecting and measuring select cells increases
Solution Approach 1:
The patent makes global bit lines multi-functional by connecting each global bit line to multiple alternating local bit lines. This allows a single global bit line to serve multiple memory cell columns, improving array utilization. The sense amplifier connected to each global bit line can detect signals from any of the associated local bit lines, maintaining detection capability despite the increased connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables fast and dynamic reading and programming of non-volatile memory cells by effectively managing voltage differentials and terminal connections, improving operational efficiency and reliability in virtual ground arrays.
Implementation Method 1
A precharging means is provided to precharge the global bit lines and local bit lines to a precharged voltage
Implementation Method 2
The state of the select non-volatile memory cell is detected by the sense amplifier connected to the global bit line
Implementation Method 3
The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell
Data Source
AI summary
A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage.