Dynamic Bit Line Voltage Adjustment for Memory Verify
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Solution Overview
Problem
In memory devices, the verify tests during programming consume time and result in read errors due to the widening of threshold voltage (Vth) distributions caused by drain-induced barrier lowering (DIBL) when using different bit line voltages for adjacent data states.
Innovation Solution
Adjusting the bit line voltages used during verify tests for memory cells assigned to upper data states by applying an elevated voltage at a minimum level and stepping it up in successive program loops, with the minimum and maximum levels and step size optimized for different pairs of adjacent data states based on data states, P-E cycles, and temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If different bit line voltages are used for adjacent data states during verify tests, then data state detection is enabled, but threshold voltage distribution widening occurs due to DIBL effect
Solution Approach 1:
The bit line voltage is made dynamic by adjusting it based on the program loop number. The voltage transitions from an initial level to a final level across successive program loops, allowing the verify test to adapt to changing threshold voltage distributions during programming. This dynamic adjustment resolves the contradiction by enabling accurate detection while accounting for DIBL-induced distribution widening at different programming stages.
Solution Approach 2:
The bit line voltage parameter is changed systematically through program loops. By varying the voltage level according to the program loop number and configuring it for different pairs of adjacent data states, the system optimizes detection accuracy while compensating for threshold voltage distribution changes. This parameter change strategy allows the verify test to maintain precision despite DIBL effects.
2Reliability
If verify tests are performed during programming, then programming completion is verified, but programming time increases
Solution Approach 1:
The verify test uses a configured bit line voltage that may be higher or lower than the standard read voltage, depending on the specific data state pair being verified. This partial adjustment of voltage conditions allows for more efficient verification by adapting to the specific programming context, reducing unnecessary time consumption while maintaining reliability.
Solution Approach 2:
By changing the bit line voltage parameter based on program loop number and data state pair, the verify operation becomes more efficient. The voltage is optimized for each verification stage, allowing faster detection of programming completion without sacrificing reliability. This parameter optimization reduces the time penalty associated with verify tests.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the widening of Vth distributions and minimizes read errors by optimizing bit line voltage settings during verify tests, ensuring accurate data state detection.
Implementation Method 1
the verify tests during programming consume time and result in read errors due to the widening of threshold voltage (Vth) distributions caused by drain-induced barrier lowering (DIBL) when using different bit line voltages for adjacent data states
Data Source
AI summary
Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.