Dynamic Bit Masking for Memory Array Write Testing
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Solution Overview
Problem
Current integrated circuit chip testing methods face challenges in efficiently testing bit write capabilities due to the need to track and store expect data for error checking, which is cumbersome and time-consuming, especially for partial writes to memory arrays.
Innovation Solution
The method involves using dynamic data bit masking to treat bit write as an 'address' function for selective data bit tests, allowing for error checking of targeted bits during testing, thereby reducing the need to store extensive bit patterns and improving test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bit write testing methods are used to ensure complete error checking, then testing reliability is improved, but test time increases and chip area for storing test results increases
Solution Approach 1:
The patent extracts only the necessary bits for comparison from the memory array by using a bit mask that selects specific bits based on address groups. Instead of reading and comparing all bits in a memory word, only the bits corresponding to the tested address group are extracted and compared, significantly reducing test time while maintaining reliability for the targeted bits.
Solution Approach 2:
The patent segments the memory array into multiple address groups, where each group is associated with specific bits that need to be tested. By dividing the memory space and selectively testing only the relevant bits in each segment, the overall test time is reduced while maintaining comprehensive coverage of all memory locations.
2Reliability
If traditional bit write testing methods are used to ensure complete error checking, then testing reliability is improved, but chip area for storing test results increases
Solution Approach 1:
The patent extracts only the necessary bits for comparison from the memory array by using a bit mask that selects specific bits based on address groups. Instead of reading and comparing all bits in a memory word, only the bits corresponding to the tested address group are extracted and compared, significantly reducing test time while maintaining reliability for the targeted bits.
Solution Approach 2:
The patent segments the memory array into multiple address groups, where each group is associated with specific bits that need to be tested. By dividing the memory space and selectively testing only the relevant bits in each segment, the overall test time is reduced while maintaining comprehensive coverage of all memory locations.
3Productivity
If dynamic bit masking is used to reduce test time and chip area, then test efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal bit masking mechanism that can be applied to any address group in the memory array. The same masking logic and comparison circuitry are used across all address groups, making the testing system multi-functional and adaptable to different memory configurations without requiring separate dedicated circuits for each address group.
Solution Approach 2:
The patent introduces a bit mask as an intermediary element that mediates between the memory array and the comparison logic. This bit mask acts as a selector that dynamically determines which bits should be compared, simplifying the overall testing architecture by decoupling the address decoding logic from the data comparison logic.
Data Source
AI summary
A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.