Dynamic Bit Adjustment in Neural Network Convolution Circuits
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Solution Overview
Problem
Existing circuit design methods for deep neural networks (DNNs) in automatic driving systems face challenges with overflow occurrences during convolution arithmetic operations, leading to increased circuit scale and delayed overflow detection, as the bit number of the convolution arithmetic unit must be adjusted based on the most severe layer conditions.
Innovation Solution
An arithmetic operation device that includes a bit reduction unit to reduce the bit strings of target data and filter weights for each convolution layer, and a bit addition unit to add the reduced bit strings to the convolution arithmetic operation result, dynamically adjusting the bit numbers to prevent overflow by shifting pixel and weight bit strings and inversely shifting the result, thereby reducing the circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit number of the convolution arithmetic unit is increased to prevent overflow, then the reliability of the arithmetic operation is improved, but the circuit mounting scale increases
Solution Approach 1:
The patent applies dynamics by making the bit number of the convolution arithmetic unit variable rather than fixed. The control unit dynamically adjusts the bit number based on the layer type and overflow determination results from previous layers, allowing the circuit to adapt its precision requirements to each specific layer's needs, thereby preventing overflow while minimizing circuit scale.
Solution Approach 2:
The patent changes the parameter of bit number from a static design-time constant to a dynamic parameter that can be adjusted during operation. By determining the appropriate bit number based on layer characteristics and overflow risk assessment, the system optimizes the balance between overflow prevention and circuit resource utilization.
2Reliability
If the circuit mounting scale is increased to accommodate the most severe layer conditions, then the reliability across all layers is improved, but the productivity of circuit design and mounting is reduced
Solution Approach 1:
The patent applies local quality by assigning different bit numbers to different convolution layers based on their specific requirements. Instead of uniformly increasing the bit number for all layers, the control unit determines the appropriate bit number for each layer individually, allowing each layer to have the precise level of precision it needs without unnecessary overhead in other layers.
Solution Approach 2:
The system dynamically determines and adjusts the bit number for each layer based on overflow determination results and layer characteristics, enabling efficient circuit design that adapts to the specific requirements of each layer rather than using a conservative one-size-fits-all approach.
3Device complexity
If overflow determination is performed after arithmetic operation in existing circuit design methods, then the device complexity is reduced, but the loss of time for detecting and responding to overflow increases
Solution Approach 1:
The patent applies preliminary action by performing overflow determination in advance before executing the arithmetic operation. The control unit determines whether overflow may occur based on layer type and previous operation results, and pre-adjusts the bit number accordingly, eliminating the need for post-operation overflow detection and correction.
Solution Approach 2:
The system uses feedback from overflow determination results and layer characteristics to dynamically adjust the bit number configuration before arithmetic operations are executed, creating a closed-loop control system that prevents overflow proactively rather than reacting to it after the fact.
Data Source
AI summary
An arithmetic operation device causes a convolution arithmetic unit to perform a convolution arithmetic operation between a filter and target data corresponding to a size of the filter in each of a plurality of convolution layers constituting a neural network. The arithmetic operation device includes: a bit reduction unit that reduces a bit string corresponding to a first bit number from a least significant bit of the target data and reduces a bit string corresponding to a second bit number from a least significant bit of a weight that is an element of the filter for each convolution layer; and a bit addition unit that adds a bit string corresponding to a third bit number obtained by adding the first bit number and the second bit number to a least significant bit of a convolution arithmetic operation result output from the convolution arithmetic unit by inputting the target data and the weight after being reduced by the bit reduction unit to the convolution arithmetic unit.