Dynamic Bit Shift Processing Device for Heterogeneous Data
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Solution Overview
Problem
Existing floating point units (FPUs) are limited in their ability to perform operations on data in heterogeneous formats, such as floating point and integer representations, leading to unnecessary memory usage and computational waste, especially in large artificial neural networks.
Innovation Solution
A bit pattern operation method using dynamic bit shift, which determines whether to perform shifts for exponent alignment and performs binary operations on bit patterns after shifting, allowing for operations between data in different formats without the need for conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If floating point units are used to perform operations on heterogeneous data formats, then computational capability is maintained, but memory usage and computational resources are unnecessarily wasted
Solution Approach 1:
The patent changes the operational parameters of the floating point unit by enabling it to directly process integer formats in addition to floating point formats. This parameter change allows the unit to operate on heterogeneous data without conversion, reducing the computational overhead and resource waste associated with format conversion while maintaining full computational capability.
Solution Approach 2:
The floating point unit is designed to perform multiple functions by supporting both floating point and integer format operations natively. This multi-functionality eliminates the need for separate conversion units and allows the same hardware resource to handle diverse data types efficiently, reducing both memory usage and computational resource waste.
2Adaptability or versatility
If data is converted to floating point representation format for operation, then operational compatibility is ensured, but computing resources are unnecessarily wasted
Solution Approach 1:
The floating point unit is enhanced to universally handle both floating point and integer formats through native support for heterogeneous operations. This eliminates the need for separate conversion pathways and reduces the overall device complexity by consolidating format handling capabilities within a single unit.
3Measurement precision
If floating point representation format is used, then precision is maintained, but memory usage increases
Solution Approach 1:
The patent changes the memory storage parameter by allowing integer formats to be stored and processed directly without conversion to floating point format. This parameter change reduces memory usage since integer formats require fewer bits than floating point representation, while the floating point unit maintains precision through its enhanced ability to handle heterogeneous formats natively.
4Adaptability or versatility
If format conversion is performed before operation, then operational compatibility is achieved, but computational time is wasted
Solution Approach 1:
The floating point unit performs preliminary preparation by natively supporting both floating point and integer formats, eliminating the need for preliminary format conversion steps. This preliminary capability is built into the unit's architecture, allowing it to directly process heterogeneous data without time-consuming conversion operations.
Solution Approach 2:
The operational parameter of the floating point unit is changed to enable direct processing of integer formats alongside floating point formats. This parameter change removes the time loss associated with format conversion by allowing the unit to operate on both formats simultaneously without requiring preliminary conversion steps.
Data Source
AI summary
A processing device may include multiplier circuitry configured to output a product of an integer represented by the first signal and a mantissa represented by the second signal. The processing device may further include a dynamic shifting circuit configured to shift a first shifted signal generated by shifting a mantissa part of a third signal based on the integer part of the first signal to generate and output a second shifted signal, and shift an output signal of the multiplier circuitry based on the integer part of the first signal to generate and output a third shifted signal. The processing device may further include an arithmetic logic circuit configured to output an signal representing a mantissa of a sum of a product of the first and second signals and the third signal based on output signals of the dynamic shifting circuit.