Dynamic Bitscan Control for Memory Programming Efficiency
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Solution Overview
Problem
Existing memory device programming techniques often result in unnecessary verify operations and program pulses, leading to inefficiencies and potential program disturb, particularly when using single-state or n-state bitscans without adapting to the actual programming state changes.
Innovation Solution
Implementing dynamic variable state bitscans that switch between performing n-state and m-state bitscans based on predetermined criteria and average threshold voltage changes, allowing for selective activation of single-state or dynamic variable state bitscans after each programming pulse to optimize programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If single-state or n-state bitscans are used without adapting to actual programming state changes, then the programming process is simpler to implement, but unnecessary verify operations and program pulses occur leading to program disturb
Solution Approach 1:
The patent implements dynamic variable state bitscans that adapt the bitscan state based on actual programming state changes. The system transitions between different bitscan states (e.g., from n-state to m-state bitscans) based on predetermined criteria and average threshold voltage changes, making the verification process dynamic rather than static. This resolves the contradiction by maintaining simplicity through automated adaptation without requiring complex manual intervention.
Solution Approach 2:
The system uses feedback from threshold voltage measurements to dynamically adjust the bitscan strategy. By monitoring average threshold voltage changes and comparing them against predetermined criteria, the system determines whether to continue with n-state bitscans or switch to m-state bitscans. This feedback mechanism eliminates unnecessary verify operations while preventing program disturb, resolving the contradiction between operational simplicity and harmful effects.
2Reliability
If fixed n-state bitscans are performed after each programming pulse, then the verification process is consistent and reliable, but unnecessary verify operations occur reducing programming efficiency
Solution Approach 1:
The patent transforms the static fixed n-state bitscan approach into a dynamic variable state bitscan system. The system automatically adjusts the bitscan state based on real-time monitoring of threshold voltage changes and predetermined criteria. This dynamic adaptation maintains verification reliability by continuing thorough checks when needed while eliminating unnecessary operations to improve programming efficiency.
Solution Approach 2:
The system changes the parameter of bitscan state (from fixed n-state to variable n-state or m-state) based on programming progress. By monitoring threshold voltage changes and adjusting the bitscan state accordingly, the system maintains reliable verification when programming is incomplete while improving efficiency by reducing unnecessary verify operations when programming is complete or making sufficient progress.
3Productivity
If dynamic variable state bitscans are implemented to reduce unnecessary operations, then programming efficiency improves, but the device complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the bitscan system automatically adjusts its own state based on predetermined criteria and threshold voltage measurements. The system performs self-diagnosis by monitoring programming progress and autonomously decides whether to continue with n-state bitscans or switch to m-state bitscans without requiring complex external control logic. This reduces device complexity while maintaining programming efficiency improvements.
Solution Approach 2:
The feedback mechanism uses predetermined criteria and average threshold voltage change measurements to automatically control the bitscan state transitions. By establishing clear feedback rules in advance, the system manages complexity through structured decision-making rather than requiring complex real-time control logic, thereby improving programming efficiency without excessive device complexity.
4Measurement precision
If more verify operations are performed to ensure accurate programming completion, then programming accuracy improves, but time consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of verification operations based on actual programming state. The system transitions between different bitscan states (n-state and m-state bitscans) based on predetermined criteria and threshold voltage changes. This dynamic approach ensures high measurement precision for programming completion accuracy when needed while reducing time consumption by eliminating unnecessary verify operations when programming is complete or making sufficient progress.
Solution Approach 2:
The system changes the verification parameter (bitscan state) based on programming progress and threshold voltage measurements. By monitoring average threshold voltage changes and comparing against predetermined criteria, the system adjusts the verification intensity dynamically. This ensures accurate programming completion detection while minimizing time loss through reduced unnecessary verify operations.
Data Source
AI summary
An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.