Dynamic Bitscan for Faster Non-Volatile Memory Verification
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Solution Overview
Problem
The programming process in non-volatile memory is time-consuming due to the substantial duration required for bitscans during the verification of memory cells, particularly when dealing with variations in physical characteristics and programming speeds across different regions of the memory structure.
Innovation Solution
Implementing a dynamic bitscan method that performs a first bitscan on a first strict subset of memory cells, followed by a determination to skip a second bitscan based on the results, optimizing the process by strategically ordering bitscans based on programming speed, thereby reducing overall programming time while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complete bitscan is performed on all memory cells to ensure verification accuracy, then measurement precision is improved, but duration of action increases significantly
Solution Approach 1:
The patent divides memory cells into multiple groups based on their programming speeds, with faster programming cells forming a first group and slower programming cells forming a second group. This segmentation allows the system to perform bitscan operations on different groups at different times, reducing the total verification time while maintaining accuracy.
Solution Approach 2:
The patent performs a preliminary bitscan on the first group of faster programming cells before programming the second group of slower programming cells. This preliminary action allows the system to identify and lock out cells that have successfully programmed, so that when the second group is programmed, only the remaining cells need to be verified, significantly reducing the overall verification time.
2Measurement precision
If multiple bitscans are performed sequentially to verify all data states, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent implements a dynamic verification approach where the system adapts its behavior based on real-time programming status. After the first bitscan identifies successfully programmed cells, the system dynamically adjusts the verification process by skipping bitscan operations on cells that are confirmed to be properly programmed, thereby reducing unnecessary verification time while maintaining completeness.
Solution Approach 2:
The patent uses feedback from the first bitscan results to control subsequent verification operations. The lockout status information obtained from the first bitscan is fed back to determine whether additional bitscan operations are necessary, allowing the system to eliminate redundant verification steps and reduce overall programming time.
Data Source
AI summary
Technology is disclosed herein for a dynamic bitscan. The dynamic bitscan may include performing a first bitscan of a first strict subset of memory cells. Then, based on results of the first bitscan, a determination is made whether to perform a second bitscan of a second strict subset of memory cells. Prior to the bitscan(s) a verify reference voltage may be applied to both strict subsets of memory cells. Skipping the second bitscan saves considerable time. However, the second bitscan is performed at least sometimes, which increases accuracy. The first strict subset of memory cells and the second strict subset of memory cells may have different locations relative to some point in the block that contains the memory cells. The first strict subset of memory cells and the second strict subset may have different programming speeds.