Dynamic Body Bias Control for Memory Read Write Margins
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Solution Overview
Problem
As semiconductor technology scales towards smaller sizes and lower power supply voltages, volatile memory elements in integrated circuits face decreased read and write margins, posing challenges for reliable device operation.
Innovation Solution
The implementation of body bias control circuitry that supplies adjustable body bias voltages to transistors in cross-coupled inverters, allowing for dynamic control of NMOS and PMOS transistors to improve read and write margins by selectively forward or reverse biasing them based on operation type and logic value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If lower power supply voltages are used to power integrated circuits, then power consumption is reduced, but read and write margins for volatile memory elements decrease
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the body bias voltage of transistors to compensate for reduced read and write margins. Specifically, reverse body bias is applied during read operations to strengthen the pull-down network, and forward body bias is applied during write operations to strengthen the pull-up network, thereby maintaining reliable operation at lower power supply voltages
Solution Approach 2:
The patent implements dynamics by making the body bias voltage time-varying and operation-dependent. The body bias control circuitry dynamically switches between different bias conditions based on whether the memory cell is being read or written, allowing the transistor characteristics to adapt in real-time to operational requirements and maintain adequate margins despite lower supply voltages
2Area of moving object
If semiconductor devices are scaled towards smaller sizes, then device density is increased, but read and write margins for volatile memory elements decrease
Solution Approach 1:
The patent uses parameter changes by adjusting the body bias voltage to compensate for the reduced transistor strength resulting from scaling. The reverse body bias during reads and forward body bias during writes modifies the transistor threshold voltages and current characteristics, counteracting the margin degradation caused by smaller device dimensions
Solution Approach 2:
The patent applies local quality by selectively applying different body bias conditions to specific transistors based on their role in the memory cell operation. The address transistors receive dynamic body bias control tailored to their specific function during read or write operations, optimizing their performance locally rather than uniformly across all devices
Data Source
AI summary
An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.