Dynamic Boosting Circuit for NAND EEPROM Voltage Stability
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Solution Overview
Problem
Conventional power supply circuits for NAND EEPROMs face challenges in achieving both high boosting capability and low output voltage fluctuations, particularly at low set voltage levels, as increasing boosting capability leads to larger circuit sizes and increased voltage fluctuations.
Innovation Solution
A power supply circuit with a boosting circuit, voltage detecting circuit, and clock signal generating circuit that dynamically adjusts the boosting capability based on detected voltage levels, using MOS transistors, capacitors, diodes, and logic circuits to control the output voltage and clock signals, thereby reducing fluctuations while maintaining high rising speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the boosting capability is increased to achieve higher rising speed of output voltage, then the voltage can be increased within predetermined time, but fluctuations in output voltage increase
Solution Approach 1:
The patent applies dynamics by making the boosting capability adjustable rather than fixed. The boosting circuit can dynamically change its boosting capability based on operating conditions, allowing it to provide strong boosting when needed (for fast rising speed) while reducing boosting strength when the output voltage is close to the target (to minimize fluctuations). This is achieved through controllable switches that adjust the effective capacitance and resistance in the boosting circuit.
Solution Approach 2:
The patent changes physical parameters of the boosting circuit, specifically the effective capacitance and resistance values, to optimize performance. By adjusting these parameters based on the voltage level and operational phase, the circuit can achieve both fast rising speed (when large capacitance/discharge is needed) and low fluctuations (when small adjustments are needed near the target voltage).
2Power
If the size of boosting circuit components is increased to guarantee high set voltages, then high voltage output is achieved, but fluctuations in output voltage at low set voltages increase
Solution Approach 1:
The patent makes the boosting circuit dynamically adjustable, allowing it to operate in different modes. When high voltage output is needed, the full boosting capability is engaged. When operating at lower set voltages, the circuit reduces its boosting strength to minimize fluctuations, thus avoiding the problem of large fluctuations that occur with fixed high-capability boosting circuits at low voltage levels.
Solution Approach 2:
The patent applies different boosting strengths to different operating conditions. Instead of using a uniform high-capability boosting circuit for all voltage levels, the circuit provides strong boosting only when high voltage is required, and reduces boosting strength at lower voltage levels where fluctuations are more problematic. This localized adjustment of boosting quality resolves the contradiction between power capability and stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively reduces output voltage fluctuations while increasing the rising speed of the output voltage, optimizing performance for NAND EEPROMs by dynamically adjusting boosting capability in response to voltage levels.
Implementation Method 1
a first capacitor having one end connected to an other end of the first MOS transistor; a second capacitor having one end connected to an other end of the fourth MOS transistor
Implementation Method 2
a first diode having an anode connected to the one end of the second MOS transistor; a second diode having an anode connected to a cathode of the first diode and a cathode connected to the output terminal
Data Source
AI summary
A power supply circuit that outputs a set voltage from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage; and a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal.