Dynamic Boosting Circuit for NAND Flash Memory Power Efficiency
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Solution Overview
Problem
Conventional NAND flash memory boosting circuits face increased current dissipation and peak current due to the need for multiple boosting stages, leading to inefficiencies and chip area expansion, especially when generating various boosted voltages for reliable operation.
Innovation Solution
The boosting circuit dynamically adjusts the number of stages based on whether a high or low voltage is being output, allowing for efficient sharing of boosted voltages without degrading power efficiency or increasing chip area, by utilizing a configuration with separate low and high boosting stages and a switch circuit to optimize the number of diode-connected transistors based on output voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple boosting circuits are used to generate various boosted voltages for reliable operation, then voltage supply reliability is improved, but current dissipation and peak current increase
Solution Approach 1:
The patent implements a universal boosting circuit that can generate multiple different boosted voltages (first, second, third, and fourth boosted voltages) through a single circuit structure. The circuit uses switch elements to selectively connect different capacitors in series, allowing one boosting circuit to perform the function of multiple dedicated boosting circuits, thereby reducing current dissipation while maintaining voltage supply reliability.
2Reliability
If multiple boosting circuits are used to generate various boosted voltages, then voltage supply reliability is improved, but chip area increases
Solution Approach 1:
The patent implements a universal boosting circuit that can generate multiple different boosted voltages (first, second, third, and fourth boosted voltages) through a single circuit structure. The circuit uses switch elements to selectively connect different capacitors in series, allowing one boosting circuit to perform the function of multiple dedicated boosting circuits, thereby reducing chip area while maintaining voltage supply reliability.
3Area of stationary object
If a single boosting circuit is used to share multiple voltages, then chip area is reduced, but power efficiency degrades
Solution Approach 1:
The patent employs a dynamic configuration where the boosting circuit can adaptively change its structure based on the required output voltage. Switch elements dynamically reconfigure the series connection of capacitors to match the demanded voltage level, ensuring optimal power efficiency for each operating condition while maintaining a compact single-circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces current dissipation and peak current while maintaining efficient power delivery, minimizing chip area and noise sources, and optimizing power efficiency across different output voltage levels.
Implementation Method 1
a boosting circuit which boosts a power supply voltage and outputs a boosted voltage
Implementation Method 2
including a first capacitor connected between a gate of the first MOS transistor and the first clock terminal
Data Source
AI summary
A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.