Dynamic Buffer Allocation for System on Chip Memory Optimization
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Solution Overview
Problem
The existing system on chip (SoC) designs require a large and expensive memory array with static buffers for each data stream, leading to inefficient use of on-chip memory resources due to the assumption of peak data bandwidth for each virtual channel, resulting in buffers often being largely empty despite receiving the same total data rate.
Innovation Solution
Implementing a dynamic memory allocation scheme using a memory control unit that adjusts buffer sizes based on data accumulation rates, allowing memory to be reallocated among buffers, thereby optimizing memory usage by ensuring only the necessary capacity is allocated for each data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer with fixed capacity is provided separately for each data stream, then each data source can operate independently with assumed full bandwidth, but the total memory size becomes excessively large and buffers remain largely empty
Solution Approach 1:
The patent implements dynamic buffer allocation where the memory capacity assigned to each virtual channel is not fixed but adjusts based on actual data accumulation rates. The buffer manager continuously monitors data flow characteristics and reallocates memory regions among virtual channels dynamically, allowing the system to adapt to varying traffic patterns and eliminate the need for oversized static buffers
Solution Approach 2:
The patent creates a shared memory pool that serves multiple virtual channels simultaneously, rather than dedicating separate fixed buffers to each channel. This universal memory resource can be allocated to any virtual channel that needs it, allowing the same physical memory to fulfill multiple functions and serve different data streams at different times based on actual demand
2Reliability
If static buffers are allocated for each virtual channel based on peak bandwidth assumptions, then data loss is prevented under peak conditions, but power consumption increases and memory resources are wasted
Solution Approach 1:
The patent changes the parameter of buffer capacity from a static fixed value to a dynamic variable that adjusts based on actual data accumulation rates. The buffer manager modifies memory allocation parameters in real-time, scaling buffer sizes up or down according to traffic conditions, thereby reducing power consumption during low-traffic periods while maintaining adequate capacity when needed
3Ease of operation
If each virtual machine assumes it can use the full bandwidth of the physical channel, then simplified operation is achieved, but the total buffer size becomes proportional to the number of virtual machines
Solution Approach 1:
The patent introduces a buffer manager as an intermediary component that sits between the virtual machines and the physical data channel. This mediator handles the complexity of buffer allocation and monitoring, allowing virtual machines to operate simply with the assumption of full bandwidth availability while the buffer manager transparently manages the actual memory distribution and prevents data loss
Data Source
AI summary
A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers.A method of operating a system on chip is also described.