Dynamic Buffer Credit Allocation for Fibre Channel Control Units

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In Fibre Channel architectures, data overflow occurs at control units due to high data transfer rates exceeding processing capabilities, leading to storage area network congestion and inefficient buffer management, particularly during long-distance high-performance operations.

Innovation Solution

A method where a control unit dynamically adjusts buffer credits based on monitoring transfer ready and retry operations across multiple channels, optimizing buffer allocation to prevent overflow and maintain high data transfer rates by increasing credits for high transfer ready operations and decreasing them for high retry operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred at high rates to I/O devices, then data transfer speed is improved, but data overflow occurs at control units exceeding their processing capabilities

Engineering Contradiction:
Improvedata transfer rateVSAvoidbuffer overflow prevention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements dynamic buffer credit allocation where the control unit monitors data transfer rates and processing capabilities in real-time, adjusting the number of buffer credits allocated to each channel accordingly. This dynamic adjustment allows the system to maintain high data transfer rates when control units can keep up, while preventing overflow by reducing credits when processing capacity is exceeded.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control unit employs a feedback mechanism by monitoring data transfer operations and buffer status, then sending updated buffer credit values back to channels. This feedback loop enables the system to adapt to changing conditions, ensuring that data transfer rates remain high when capacity is available while preventing overflow by signaling channels to slow down when buffers are full.

Inventive Principle:
Principle #23Feedback

2Productivity

If buffer credits are increased to maintain high data transfer rates, then productivity is improved, but buffer exhaustion and congestion occur when processing capacity is exceeded

Engineering Contradiction:
Improvedata transfer throughputVSAvoidbuffer overflow and network congestion
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The system dynamically adjusts buffer credit values based on real-time monitoring of control unit processing capacity and buffer status. When processing capacity is high, more credits are allocated to maximize throughput. When capacity is exceeded, credits are reduced to prevent overflow, thus dynamically balancing productivity gains against the risk of buffer exhaustion and congestion.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If static buffer credit allocation is used, then device complexity is reduced, but operational latency increases due to inability to adapt to varying processing capacities

Engineering Contradiction:
Improvebuffer management mechanismVSAvoidoperational latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The control unit performs self-monitoring of its processing capacity and buffer status, automatically adjusting buffer credit allocation without external intervention. This self-service approach allows the system to adapt to varying workloads and maintain low latency dynamically, while the adjustment logic remains integrated within the control unit, avoiding the need for complex external buffer management infrastructure.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10140236B2Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting data to a control unit
Publication Date: 2018.11.27 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10140236B2 patent drawing
  • US10140236B2 patent drawing
  • US10140236B2 patent drawing

AI summary

A channel of a host computational device sends a command to transfer data to a control unit included in a storage controller. The channel of the host computational device receives a number of buffer credits from the control unit for communication with the control unit, where the number of buffer credits that is received is based on the control unit monitoring a number of transfer ready operations and a number of retry operations during a monitoring period while communicating with a plurality of channels that includes the channel.