Dynamic Buffer Size Adjustment in Data Storage Devices

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Solution Overview

Problem

Existing data storage devices face challenges in accurately determining the optimal buffer size, leading to fluctuations in write speed and user experience, as current methods fail to dynamically adjust buffer size based on user requirements and storage capacity.

Innovation Solution

A method is introduced where a data storage device dynamically determines its buffer size by calculating the total storage capacity and configuring memory blocks based on user-set maximum write data, using a memory controller to adjust the number of memory blocks and their type to maintain optimal performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the buffer size is increased to improve write speed, then write performance is improved, but the available storage capacity for user data is reduced

Engineering Contradiction:
Improvewrite speedVSAvoidavailable storage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic buffer size adjustment by allowing the memory controller to reconfigure memory blocks between buffer and storage based on operational conditions. The buffer size is not fixed but can be dynamically modified to optimize write performance while preserving user storage capacity, directly resolving the contradiction between write speed and available storage.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If a fixed buffer size is configured to simplify device operation, then ease of operation is improved, but adaptability to different user requirements is reduced

Engineering Contradiction:
Improvedevice operation simplicityVSAvoidadaptability to user requirements
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The memory controller automatically performs buffer size optimization without requiring user intervention. The system monitors write operations and storage capacity usage, then autonomously reconfigures memory blocks to maintain optimal buffer size, achieving both ease of operation and adaptability to different usage scenarios.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the buffer size parameter dynamically based on storage capacity and write operation characteristics. By modifying this key parameter in response to system conditions, the device maintains optimal performance across different user requirements while keeping the operation transparent to users.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the buffer size is dynamically adjusted to optimize write speed, then write performance is improved, but device complexity increases

Engineering Contradiction:
Improvewrite speedVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller serves multiple functions: it manages normal memory operations, monitors storage capacity usage, determines optimal buffer sizes, and executes reconfiguration of memory blocks. By consolidating these diverse functions into a single controller component, the patent achieves dynamic buffer optimization without proportionally increasing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12099745B2Data storage device and method for dynamically determining a buffer size
Publication Date: 2024.09.24 SILICON MOTION INC
  • US12099745B2 patent drawing
  • US12099745B2 patent drawing
  • US12099745B2 patent drawing

AI summary

A data storage device includes a memory device and a memory controller. The memory device has a corresponding total storage capacity and includes multiple memory blocks. The total storage capacity is set to a maximum storage capacity provided by the memory blocks by default. The memory blocks include one or more predetermined memory blocks configured as a buffer to receive data from a host device. The memory controller is coupled to the memory device to access the memory device. In response to setting of a maximum amount of write data, the memory controller determines a value of the total storage capacity according to the maximum amount of write data, and determines a number of said one or more predetermined memory blocks according to the value of the total storage capacity and the maximum storage capacity.