Dynamic Buffer Sizing for Power Leakage Reduction
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Solution Overview
Problem
Existing computing devices face inefficiencies in power consumption due to static buffer sizing, which leads to excess power leakage, especially when components operate at different frequencies, and traditional power control methods are ineffective in such scenarios.
Innovation Solution
A system and method for dynamically controlling the size of FIFO buffers based on the activity level of components within a computing device, using a monitor module to determine use cases and adjust buffer sizes accordingly, allowing for reduced power consumption without impacting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer memories are sized for worst-case scenarios to ensure no data loss, then data transfer reliability is improved, but power consumption increases due to excess buffer capacity remaining active
Solution Approach 1:
The patent applies dynamics by making the buffer size adjustable rather than fixed. The buffer size is dynamically changed based on the operational frequencies of data transfer components - when components operate at lower frequencies, the buffer size is reduced; when higher frequencies are detected, the buffer size is increased. This resolves the contradiction by allowing the system to use smaller buffers (saving power) when worst-case scenarios don't occur, while still expanding to worst-case sizes when needed to maintain reliability.
Solution Approach 2:
The patent changes the parameter of buffer size based on operational conditions. The monitor module detects the frequencies at which data transfer components operate and uses this information to adjust buffer sizes accordingly. This parameter change allows the system to optimize between power consumption and data loss prevention by matching buffer capacity to actual operational needs rather than using a static worst-case size always.
2Use of energy by moving object
If traditional voltage/frequency control methods are used to reduce power consumption, then power savings are achieved, but these methods become ineffective when multiple components share a single power rail
Solution Approach 1:
The patent introduces an intermediary approach by using buffer size adjustment as a middle ground between voltage/frequency control and data integrity. Instead of directly controlling voltage or frequency (which becomes ineffective when components share power rails), the system uses buffer size as an intermediary mechanism to manage data transfer timing and prevent data loss, thereby achieving power savings without compromising reliability when multiple components share power infrastructure.
3Device complexity
If static buffer sizing is used throughout operation, then system complexity is reduced, but power leakage increases when components operate at lower frequencies
Solution Approach 1:
The patent implements feedback by using a monitor module that continuously detects the operational frequencies of data transfer components and uses this information to adjust buffer sizes. This feedback mechanism allows the system to respond to actual operational conditions, reducing buffer size (and power leakage) when components operate at lower frequencies while automatically increasing buffer size when higher frequencies are detected, thus optimizing power consumption without excessive complexity.
Data Source
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AI summary
Methods and systems for dynamically controlling buffer size in a computing device in a computing device ("PCD") are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a fist buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.