Dynamic Buffer Switching for 3D Display Tearing

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Solution Overview

Problem

Conventional 3D display systems experience issues such as tearing artifacts due to inadequate buffering control, especially when using cheap or low-end components, leading to poor user experience and performance.

Innovation Solution

A method and system for dynamic buffer management in a video display system, where two buffers are used as on-screen buffers for 3D frames, with the controller dynamically switching between them and additional buffers as off-screen buffers, utilizing a demultiplexer, video decoders, and a buffering module to maintain performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional buffering control is used in 3D display systems, then the system can operate with simple hardware components, but tearing artifacts occur and display quality deteriorates

Engineering Contradiction:
Improvedisplay qualityVSAvoidbuffering control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic buffer switching where the controller alternates between first and second buffers for storing 3D video frames based on timing signals. This dynamic allocation prevents tearing artifacts by ensuring that each buffer is fully written before being read, eliminating the need for complex hardware while maintaining high display quality

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The buffering function is segmented into separate first and second buffers, with dedicated write and read operations for each. This segmentation allows independent control of frame storage and display operations, preventing data corruption and tearing artifacts while keeping the overall system architecture simple

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If cheap or low-end hardware components are used, then manufacturing cost is reduced, but display performance and user experience deteriorate

Engineering Contradiction:
Improvemanufacturing costVSAvoiddisplay performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The controller automatically manages buffer allocation and switching based on timing signals without requiring external intervention or complex hardware support. This self-service approach allows low-end components to achieve high display performance through intelligent software control, eliminating the need for expensive dedicated buffering hardware

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system changes operational parameters dynamically by switching between different buffer configurations based on timing signals. This parameter change strategy allows the same simple hardware to adapt its behavior for optimal performance, achieving high reliability without increasing manufacturing cost

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If buffers are not properly controlled, then hardware resources can be minimized, but tearing artifacts occur and user experience worsens

Engineering Contradiction:
Improvehardware resourcesVSAvoidtearing artifacts
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The controller uses periodic timing signals to switch between first and second buffers in a regular cycle. This periodic action ensures that each buffer completes its write operation before being switched for reading, preventing tearing artifacts while maintaining minimal hardware resources through systematic buffer management

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8786674B2Method for performing video display control within a video display system, and associated video processing circuit and video display system
Publication Date: 2014.07.22 XUESHAN TECH INC
  • US8786674B2 patent drawing
  • US8786674B2 patent drawing
  • US8786674B2 patent drawing

AI summary

A method for performing video display control within a video display system includes: dynamically utilizing two of a plurality of buffers as on-screen buffers for three-dimensional (3D) frames, wherein the plurality of buffers is positioned within the video display system; and during utilizing any of the two of the plurality of buffers as an on-screen buffer, dynamically utilizing at least one other buffer of the plurality of buffers as at least one off-screen buffer for at least one 3D frame. An associated video processing circuit and an associated video display system are also provided. In particular, the video processing circuit is positioned within the video display system, where the video processing circuit operates according to the method.