Dynamic Bursts for Frequency-Agile Memory Interfaces
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Solution Overview
Problem
In portable computing devices, link interface circuitry between the processor and memory does not fully benefit from reduced clock speeds and voltage in power-saving modes, leading to increased power consumption per bit transferred.
Innovation Solution
Implementing a clocked memory system that supports dynamic bursts, where the link operates at a 'sweet spot' data rate and is powered down between bursts, using a clock multiplier circuit to generate a non-continuous bit clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the link interface circuitry operates continuously at reduced clock speeds in power-saving mode, then the total power consumption is reduced, but the power consumption per bit transferred increases
Solution Approach 1:
The link interface circuitry operates in periodic bursts rather than continuously. During power-saving mode, the circuitry remains idle and consumes minimal power, then activates periodically to transfer data in high-speed bursts. This periodic operation allows the system to maintain low average power consumption while achieving high data transfer rates during active periods, thereby reducing power consumption per bit transferred.
2Productivity
If the link interface circuitry operates at high data rates continuously, then productivity is improved, but power consumption increases
Solution Approach 1:
The system employs periodic burst mode operation where the link interface circuitry activates at high data rates only when data transfer is needed, then enters idle state to conserve power. This creates a rhythm of high-speed data transmission followed by low-power idle periods, achieving high productivity during active phases while minimizing overall power consumption.
Solution Approach 2:
The link interface circuitry dynamically adjusts its operational state between idle and active modes based on data transfer requirements. The circuitry transitions from a low-power idle state to a high-performance active state only when needed, optimizing the balance between productivity and power consumption by adapting its operational characteristics to real-time demands.
Data Source
AI summary
The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.