Dynamic Bus Arbitration for SoC Process Priority Control
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Solution Overview
Problem
In high-performance System-on-Chip (SoC) devices with multiple CPUs and IP modules, the bus bandwidth is insufficient, leading to potential crashes when all real-time IPs operate simultaneously, and existing bus arbitration technologies fail to adapt priority control based on Human Machine Interface (HMI) inputs, resulting in reduced processing performance.
Innovation Solution
A bus arbitration system that includes a process identification information holding unit and a bus arbiter capable of determining priority orders for each process, allowing for dynamic priority control based on process identification information and HMI inputs, thereby optimizing bus usage among multiple processes and CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all real-time IPs operate simultaneously in high-performance SoC, then processing capability is improved, but bus bandwidth becomes insufficient causing crashes
Solution Approach 1:
The bus arbitration system dynamically adjusts priority orders based on process identification information and HMI inputs, allowing the system to adapt bus resource allocation in real-time according to actual workload conditions, thereby preventing bus crashes while maintaining high processing capability
Solution Approach 2:
The system changes the parameter of priority order for bus arbitration based on process ID and external inputs, enabling flexible control of bus access rights to optimize the balance between processing capability and system stability
2Device complexity
If fixed priority order is assigned to CPUs and IP modules, then bus arbitration is simplified, but processing performance is reduced due to inability to adapt to different application requirements
Solution Approach 1:
The bus arbitration system transitions from static to dynamic priority assignment, where priority orders are determined based on process identification information and can be adjusted according to HMI inputs, thereby improving processing performance without significantly increasing system complexity
Solution Approach 2:
The bus arbiter acts as an intermediary that introduces process identification information as a new parameter for arbitration, enabling flexible priority control without requiring complex modifications to the underlying bus architecture or IP module designs
3Ease of operation
If same priority order is given to all processes, then bus arbitration is straightforward, but processing performance is reduced due to bottlenecks in high workload conditions
Solution Approach 1:
The system introduces process identification information as a new parameter for bus arbitration, enabling the bus arbiter to differentiate priority orders for different processes dynamically, thereby resolving bottlenecks while maintaining straightforward arbitration logic
Data Source
AI summary
To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.