Dynamic Cache Line Allocation via Store Instruction Specifiers
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Solution Overview
Problem
Current data processing systems employ static cache line allocation policies, which fail to optimize system performance as they either never or always allocate a new cache line on write misses, leading to suboptimal performance.
Innovation Solution
Implementing a dynamic cache line allocation policy through the use of an allocation policy specifier within processor store instructions, allowing for per-access control of cache line allocation, enabling override of static policies and specifying whether to allocate a new cache line or write directly to memory on cache misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a static cache line allocation policy is used (either always allocate or never allocate on write miss), then the system structure is simple and easy to implement, but system performance is suboptimal
Solution Approach 1:
The patent transforms the static cache allocation policy into a dynamic one by introducing an allocation policy specifier field in store instructions. This allows the allocation behavior (allocate or do not allocate cache line) to be dynamically selected on a per-instruction basis, enabling the system to adapt to different access patterns while maintaining implementation simplicity through hardware-supported instruction encoding.
Solution Approach 2:
The patent changes the allocation policy parameter from a fixed system-wide setting to a per-instruction variable. The allocation policy specifier field in the store instruction encodes different allocation policies, allowing the system to switch between allocation and non-allocation behaviors based on the specific instruction characteristics and access patterns, thereby optimizing performance without excessive complexity.
2Reliability
If cache line allocation is always performed on write miss, then subsequent accesses to the same data may benefit from cache hits, but unnecessary cache allocations increase memory usage and reduce cache effectiveness
Solution Approach 1:
The patent applies different allocation behaviors to different store instructions based on their local characteristics. The allocation policy specifier in each instruction allows the system to make localized decisions about cache allocation, allocating cache lines only for instructions that benefit from temporal locality while avoiding allocation for instructions that do not, thus optimizing both cache hit rate and memory usage.
3Quantity of substance
If cache line allocation is never performed on write miss, then cache memory is preserved for other uses, but subsequent accesses to the same data cannot benefit from cache hits
Solution Approach 1:
The patent enables selective cache allocation at the instruction level through the allocation policy specifier. This allows the system to allocate cache lines locally for specific instructions that exhibit temporal locality patterns, while leaving cache memory available for other uses in instructions that do not require allocation, thus balancing cache hit rate improvement with cache memory availability.
Data Source
AI summary
A processing system and method performs allocation of memory cache lines in response to a cache write miss. A processor receives a plurality of data processing instructions. A first store instruction for storing data in a system memory at a predetermined address is decoded by decoding a first specifier within the first store instruction. The first specifier determines an allocation policy for the first store instruction wherein the allocation policy determines whether to store data within the cache when the predetermined address is not within the cache. Additional store instructions are decoded. For example, a second specifier determines an allocation policy for a second store instruction. The specifier in each of the store instructions may be implemented in various forms to provide a policy indicator for each store instruction. No allocation policy may also be established on a per-access basis.