Dynamic Cache Allocation Policy Adaptation in Data Processing
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Solution Overview
Problem
In data processing apparatuses, the no-write allocate cache policy can lead to inefficiencies when memory transactions require writing to specific ranges of memory addresses, as it may not cache data items that could benefit from being stored locally, due to constraints like error correction codes or hardware configurations that necessitate writing entire groups of data items.
Innovation Solution
A data processing apparatus that dynamically switches between no-write allocate and write allocate cache policies based on an access undersize condition, where the cache unit stores local copies of data items when write access requests partially cover predetermined ranges of memory addresses, allowing for caching without significantly increasing bus transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a no-write allocate policy is used to avoid additional bus activity, then bus transaction burden is reduced, but data caching efficiency deteriorates when write access requests partially cover memory address ranges
Solution Approach 1:
The cache allocation policy is made dynamic by switching between no-write allocate and write allocate modes based on the access undersize condition. When the condition is detected (partial coverage of memory address ranges), the policy transitions to write allocate to improve caching efficiency. This dynamic adaptation resolves the contradiction by allowing the system to optimize for bus reduction in normal operation while switching to caching optimization when beneficial opportunities arise.
Solution Approach 2:
The system changes the cache allocation parameter (policy mode) based on the detected access pattern. When write access requests partially cover predetermined memory address ranges, the parameter switches from no-write allocate to write allocate mode. This parameter change enables the system to capture caching benefits without permanently increasing bus transaction burden, as the switch is conditional and targeted.
2Productivity
If a write allocate policy is used to cache data items, then data caching efficiency is improved, but bus transaction burden increases due to retrieving entire cache lines
Solution Approach 1:
Instead of always performing full cache line retrieval (excessive action), the system applies write allocate policy selectively only when the access undersize condition is met. This partial application of the write allocate policy captures the essential benefit of caching (improved productivity) while avoiding the excessive bus transactions that would occur with unconditional write allocate. The action is calibrated to match the actual need.
Solution Approach 2:
The cache allocation policy dynamically switches between no-write allocate and write allocate modes based on runtime conditions. This dynamic behavior allows the system to achieve high data caching efficiency only when beneficial (when write requests partially cover memory ranges), while maintaining low bus transaction burden during other operations. The dynamic switching resolves the contradiction by making write allocate conditional rather than constant.
3Loss of energy
If the cache unit operates with a fixed no-write allocate policy, then bus activity is minimized, but adaptability to different access patterns deteriorates
Solution Approach 1:
The cache allocation policy is transformed from a fixed static configuration to a dynamic adaptive one. The system continuously monitors write access requests and detects access undersize conditions, then switches between no-write allocate and write allocate modes accordingly. This dynamic adaptation enables the cache to respond to different access patterns (sequential, random, partial coverage) while maintaining low bus activity as the default behavior. The principle of dynamics directly resolves the contradiction between fixed policy simplicity and adaptive responsiveness.
Solution Approach 2:
The system implements feedback by monitoring the characteristics of write access requests (whether they partially cover predetermined memory address ranges) and using this information to adjust the cache allocation policy. When the feedback indicates an access undersize condition, the policy switches to write allocate; otherwise, it maintains no-write allocate. This feedback mechanism enables adaptability to different access patterns while keeping bus activity minimized under normal conditions, resolving the contradiction between fixed policy and adaptive behavior.
Data Source
AI summary
A data processing apparatus and method of processing data are disclosed according to which a processor unit is configured to issue write access requests for memory which are buffered and handled by a memory access buffer. A cache unit is configured, in dependence on an allocation policy defined for the cache unit, to cache accessed data items. Memory transactions are constrained to be carried out so that all of a predetermined range of memory addresses within which one or more memory addresses specified by the buffered write access requests lie must be written by the corresponding write operation. If the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses, and the cache unit is configured to operate with a no-write allocate policy, the data processing apparatus is configured to cause the cache unit to subsequently operate with a write allocate policy.