Dynamic Cache Area Allocation for Server Processors

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Solution Overview

Problem

In multitasking server processors, the fixed allocation of dedicated cache areas for specific processing tasks leads to inefficient use of cache memory, as it is difficult to predict which applications will be executed, and the current methods result in increased program development steps and wasteful allocation of resources.

Innovation Solution

A dynamic cache area allocation method where the processor allocates dedicated cache areas based on memory access frequency and cache hit rates, allowing for reallocation and release of cache areas during process execution to optimize cache usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated cache areas are fixedly allocated for specific processing tasks, then cache hit rates for those tasks are improved, but cache memory utilization efficiency deteriorates due to unpredictable application execution patterns

Engineering Contradiction:

Improvecache hit rateVSAvoidcache memory utilization efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic cache area allocation where the cache memory is divided into shared areas and dedicated areas that can be flexibly adjusted based on runtime conditions. The control unit monitors application execution patterns and dynamically reallocates cache areas between shared and dedicated portions, allowing the system to adapt to unpredictable application patterns while maintaining high cache hit rates for active processes.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the allocation parameters of cache memory dynamically based on runtime monitoring data. The control unit adjusts the size and assignment of dedicated cache areas according to observed memory access patterns and application behavior, transforming the static allocation into a dynamic parameter that optimizes both cache hit rates and overall utilization efficiency.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If dedicated cache areas are allocated for all types of processing, then cache performance is improved, but resource wastage increases due to allocation of cache areas for processing that does not require them

Engineering Contradiction:

Improvecache performanceVSAvoidresource wastage

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The patent applies partial allocation of dedicated cache areas only to processing tasks that demonstrably require them, rather than allocating dedicated areas to all processes. The control unit identifies specific processing tasks with high memory access demands and allocates dedicated cache areas only to those, leaving other tasks to use shared cache areas, thus avoiding resource wastage while maintaining performance for critical tasks.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The system enables processing tasks to effectively request and receive dedicated cache resources based on their actual needs. The control unit monitors memory access patterns and automatically allocates dedicated cache areas to tasks that exhibit characteristics requiring dedicated resources, allowing the system to self-regulate resource allocation without external intervention or pre-programming.

Inventive Principle:

Principle #25Self-service

3Ease of manufacture

If fixed allocation of dedicated cache areas is implemented, then program development steps are simplified, but adaptability to different application patterns deteriorates

Engineering Contradiction:

Improveprogram development stepsVSAvoidadaptability to different application patterns

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements a self-managing cache allocation system where the control unit automatically monitors application behavior and adjusts cache area allocation without requiring program modifications or developer intervention. The system adapts to different application patterns dynamically by detecting memory access characteristics and reallocating cache resources accordingly, maintaining ease of use while providing high adaptability.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The system incorporates continuous feedback loops where the control unit monitors memory access patterns, cache hit rates, and application behavior in real-time. Based on this feedback, the control unit dynamically adjusts dedicated cache area allocation to match actual application needs, enabling the system to adapt to different application patterns without requiring pre-programming or developer knowledge of specific application requirements.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9734075B2Cache memory control program, processor incorporating cache memory, and cache memory control method

Publication Date: 2017.08.15 FUJITSU LTD

AI summary

A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area.