Dynamic Cache Data Block Sizing for Memory Access
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Solution Overview
Problem
Conventional cache memory systems are inflexible in data access, as they read fixed-sized data blocks from main memory during cache misses, leading to inefficient utilization of cache memory resources.
Innovation Solution
A memory data access method and apparatus that dynamically adjusts the size of data blocks read from main memory based on a pre-determined memory address range and corresponding data access amount, allowing for flexible utilization of cache memory by reading data blocks of varying sizes and writing them into the cache memory for future access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed-sized data blocks are read from main memory during cache misses, then the cache memory structure is simple and easy to implement, but the cache memory utilization is inefficient and inflexible
Solution Approach 1:
The patent implements dynamic adjustment of data block sizes by introducing a memory address range register and data access amount register that can be programmatically configured. The processing unit dynamically determines the appropriate data block size based on the memory address range and access amount parameters, allowing the cache system to adapt to different access patterns rather than using a fixed block size. This resolves the contradiction by making the system flexible (improving adaptability) while maintaining a relatively simple hardware structure through register-based control (limiting complexity increase).
Solution Approach 2:
The patent changes the parameter of data block size from a fixed value to a variable determined by memory address range and access amount. By introducing configurable parameters (memory address range register and data access amount register), the system can adjust the data block size to match actual access patterns. This parameter change enables efficient cache utilization for both sequential and random access patterns while keeping the implementation straightforward through register-based parameter storage and comparison logic.
2Adaptability or versatility
If larger data blocks are read from main memory, then the cache memory utilization improves, but the main memory access time increases
Solution Approach 1:
The patent applies partial action by reading exactly the amount of data needed (specified by the data access amount register) rather than always reading full cache lines or fixed-sized blocks. This allows the system to read only the necessary portion of data from main memory, avoiding the time penalty of reading excessive data that won't be used. The memory address range register ensures that only relevant data within the specified range is accessed, optimizing the balance between cache utilization and access time.
3Productivity
If dynamic adjustment of data block sizes is implemented, then cache memory utilization and access efficiency improve, but the control logic complexity increases
Solution Approach 1:
The patent introduces intermediary components (memory address range register and data access amount register) that mediate between the processing unit and the cache memory system. These registers serve as intermediaries that store the parameters needed for dynamic data block size determination, simplifying the control logic by separating parameter storage from the data access execution. The processing unit writes the parameters to these intermediary registers, and the cache control logic simply reads and uses them, reducing the overall control complexity while maintaining dynamic adjustment capability.
Data Source
AI summary
The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.