Dynamic Cache Budget Scheduling for Multi-Core Cache Contention
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Solution Overview
Problem
In multi-core processing devices, cache memory allocation is inefficient due to competition among processor cores, leading to performance disadvantages and reduced cache hit ratios, as existing methods do not consider task characteristics or execution environments.
Innovation Solution
A method and device for dynamically allocating cache areas based on task characteristics and execution environments, including memory access patterns, priorities, and current consumption, to adaptively set cache sizes for individual processor cores, reducing core competition and enhancing cache efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache memory is shared among multiple processor cores, then memory utilization is improved, but cache hit ratio deteriorates due to competition among cores
Solution Approach 1:
The patent divides the shared cache memory into multiple cache areas, with each area dedicated to specific processor cores. This localizes the cache resources to reduce interference between different core groups while maintaining overall shared memory utilization. Processor cores are classified into different groups based on their task characteristics and memory access patterns, and each group is assigned specific cache areas to minimize competition.
Solution Approach 2:
The cache memory is segmented into multiple cache areas that can be dynamically allocated to different processor core groups. This segmentation allows the system to balance between shared utilization and dedicated access by creating separate cache regions for different core groups, thereby reducing cache conflicts while maintaining high utilization across the entire cache memory.
2Reliability
If cache memory size is increased to reduce competition, then cache hit ratio is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements dynamic cache area allocation where the size and assignment of cache areas are adjusted in real-time based on the current execution environment, task characteristics, and memory access patterns. This dynamic approach allows the system to optimize cache hit ratio without permanently increasing cache memory size, as the same cache resources are adaptively reallocated to match changing workload demands.
Solution Approach 2:
The system changes the allocation parameters of cache areas based on monitored task characteristics and memory access patterns. By adjusting which processor cores are grouped together and which cache areas they access, the system optimizes cache performance without physical expansion. The classification and grouping parameters are dynamically modified to reflect current system state.
3Device complexity
If static cache allocation is used, then device complexity is reduced, but adaptability to different task characteristics deteriorates
Solution Approach 1:
The system automatically monitors task characteristics and memory access patterns, and autonomously performs classification and cache area allocation without requiring external intervention. The monitoring logic circuitry continuously gathers execution environment data, and the cache budget scheduling circuitry automatically adjusts cache allocations based on this data, enabling the system to adapt to different task characteristics while maintaining relatively simple hardware architecture.
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors memory access patterns and task characteristics, then uses this information to adjust cache area allocations. The monitoring logic provides feedback to the cache budget scheduling circuitry, which adjusts cache assignments based on observed performance and access patterns, creating a closed-loop system that adapts to changing workload requirements.
Data Source
AI summary
A method is provided. The method includes: receiving a plurality of characteristic information associated with a plurality of tasks allocated to a plurality of processor cores; monitoring a task execution environment while the plurality of processor cores perform the plurality of tasks based on at least one operating condition; and allocating a plurality of cache areas of at least one cache memory to the plurality of processor cores based on the plurality of characteristic information and the task execution environment. Sizes of the plurality of cache areas are set differently for the plurality of processor cores.