Dynamic Cache Clock Control for Memory Access Latency
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Solution Overview
Problem
In CPU architectures, memory access bottlenecks occur due to cache misses, where reducing clock frequency or introducing extra latency are common solutions, but these compromise system performance.
Innovation Solution
Dynamic clock control is implemented by delaying the cache clock during cache fills from main memory, allowing more time for data transfer and maintaining full clock period for the cache to CPU path without additional latency or frequency reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the clock frequency is reduced to permit single cycle access to main memory, then cache miss latency is reduced, but the performance of the entire data processing system deteriorates
Solution Approach 1:
The patent implements dynamic clock control where the cache clock frequency is adjusted based on operational mode: full frequency for normal cache operations, and reduced frequency during cache fill operations from main memory. This dynamic adjustment allows the system to optimize for either speed or data transfer completeness depending on the current operation, resolving the contradiction between maintaining high performance and accommodating slow memory-to-cache transfers.
2Loss of time
If an extra latency of 1 cycle is inserted in the memory to memory data path, then cache fill latency is reduced, but the cache fill time increases
Solution Approach 1:
The patent changes the clock frequency parameter dynamically based on the operational phase. During cache fill operations, the clock is slowed down to extend the duration of the fill operation, allowing complete data transfer without stalling the CPU. This parameter change resolves the contradiction by accepting longer fill time in exchange for maintaining system throughput and avoiding additional latency cycles.
3Duration of action of moving object
If the clock to the cache is delayed during cache fills from main memory, then data transfer time is increased, but the cache to central processing unit path timing is compromised
Solution Approach 1:
The patent segments the cache system into independent clock domains: the cache memory array operates on a delayed/slowed clock during fills to accommodate data transfer, while the cache control logic and CPU interface operate on the full-speed clock to maintain timing requirements. This segmentation allows both contradictory requirements to be satisfied simultaneously in different parts of the system.
Data Source
AI summary
This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation will occur. The dynamic extension of the clock signal includes delaying the clock signal, forming a waveform toggling between states upon each predetermined state transition of the delayed clock signal, selecting the clock signal when this waveform has a first stage, and selecting the delayed clock signal when this waveform has a second state. Dynamic extension is prevented during a test mode. An apparatus of this invention uses a flip-flop and a multiplexer to produce the dynamically delayed clock.