Dynamic Cache Coherence Protocol Selection via Repeat-Read Tracking

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Solution Overview

Problem

Conventional cache coherence protocols, such as write invalidate and write update protocols, are not equally efficient in all scenarios due to lack of dynamic selection mechanisms, leading to suboptimal performance and energy consumption in processor-based devices.

Innovation Solution

Implementing a dynamic selection mechanism that uses repeat-read indicators to determine whether the write invalidate or write update protocol is preferred based on the likelihood of re-reading coherence granules, allowing the central ordering point circuit to select the appropriate protocol on a store-by-store basis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the write invalidate protocol is used, then performance is improved when many subsequent memory store operations are performed by a PE, but performance deteriorates when memory load operations are performed by multiple PEs

Engineering Contradiction:
ImproveperformanceVSAvoidprotocol adaptability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic protocol selection by allowing the COP to choose between write invalidate and write update protocols on a per-store basis. The system monitors operational patterns and dynamically switches protocols to match actual workload characteristics, resolving the contradiction between optimized invalidation performance and adaptability to different access patterns.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the protocol selection parameter based on observable operational parameters such as the number of subsequent store operations and load operations. By adjusting the protocol choice according to these parameter changes in access patterns, the system achieves both high performance for sequential stores and adaptability for mixed workloads.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the write update protocol is used, then performance is improved when memory load operations are performed by multiple PEs, but performance deteriorates when many subsequent memory store operations are performed by a PE

Engineering Contradiction:
ImproveperformanceVSAvoidprotocol adaptability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The dynamic protocol selection mechanism allows the system to switch from write update to write invalidate based on observed operational patterns. When a PE performs multiple subsequent store operations, the system dynamically selects write invalidate to optimize performance, thereby resolving the contradiction between load operation performance and store operation efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses feedback from monitoring operational patterns (counts of subsequent stores and loads) to adjust protocol selection. This feedback mechanism enables the system to learn from actual workload characteristics and select the optimal protocol, achieving both high performance and adaptability.

Inventive Principle:
Principle #23Feedback

3Productivity

If a fixed cache coherence protocol is used, then device complexity is reduced, but performance becomes suboptimal in diverse scenarios

Engineering Contradiction:
ImproveperformanceVSAvoidprotocol selection complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements self-service by having the COP autonomously monitor operational patterns and select protocols without external intervention. The automatic protocol selection based on observed access patterns reduces the need for complex manual configuration while achieving optimal performance across diverse scenarios.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary monitoring and analysis of operational patterns before making protocol selection decisions. By preparing and analyzing access pattern data in advance, the system can make informed protocol choices that optimize performance without requiring complex real-time computation or configuration.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4208792B1Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices
Publication Date: 2024.06.26 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP4208792B1 patent drawingFigure 1
  • EP4208792B1 patent drawingFigure 2A
  • EP4208792B1 patent drawingFigure 2B

AI summary

Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.