Dynamic Cache Error Protection via Coherency and Bit History
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Solution Overview
Problem
Modern computing devices face significant power consumption issues in cache memory due to high electrical power usage, which can lead to bit errors at lower supply voltages, making memory circuits more susceptible to faults and errors.
Innovation Solution
Implementing a cache memory system that uses history records to dynamically select error protection based on bit error detection and coherency states, employing parity checks and error correction codes only where necessary, and dynamically mapping error protection cache entries to portions of the cache with bit errors, thereby reducing power consumption and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is lowered to reduce power consumption, then power consumption is reduced, but memory circuits become more susceptible to bit errors
Solution Approach 1:
The patent applies different error protection mechanisms to different portions of the cache based on their error history. Portions with no recorded errors use minimal protection (parity checks only), while portions with single-bit errors use stronger protection (error correction codes). This local differentiation allows the system to maintain reliability in error-prone regions while minimizing power consumption in reliable regions.
Solution Approach 2:
The patent dynamically changes the error protection parameters based on the coherency state of data and the error history of cache portions. When data is in a modifiable coherency state and the cache portion has no recorded errors, weaker protection is used. When data is in a non-modifiable state or the portion has errors, stronger protection is applied. This parameter adaptation resolves the contradiction by adjusting protection strength to match actual risk levels.
2Reliability
If error protection is applied to entire cache, then bit errors are protected, but protection overhead and design complexity increase
Solution Approach 1:
The patent divides the cache into multiple portions and maintains separate error history records for each portion. This segmentation allows the system to apply error protection selectively only to portions that need it, rather than uniformly across the entire cache. The cache controller can identify specific portions with errors and apply appropriate protection mechanisms only to those segments, reducing overall overhead and complexity.
Solution Approach 2:
The patent implements partial error protection by applying error correction codes only to cache portions that have recorded bit errors, while using simpler parity checks for portions without errors. This partial application of protection mechanisms provides sufficient reliability for error-prone regions while avoiding the excessive overhead that would result from applying full error correction across the entire cache.
3Reliability
If extensive error correction metadata is stored across entire cache, then bit errors are corrected, but power consumption and design complexity increase
Solution Approach 1:
The patent stores error correction metadata locally and selectively in the cache portion entries rather than uniformly across the entire cache. Each cache portion entry contains error history information and appropriate correction metadata only for that specific portion. This local storage approach reduces the total amount of metadata that must be maintained and accessed, thereby reducing power consumption while maintaining error correction capability where needed.
Data Source
AI summary
A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.