Dynamic Cache Extension in Heterogeneous Processors

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Solution Overview

Problem

Existing multi-cluster heterogeneous processor architectures fail to optimize performance and power consumption in use cases with wide memory access and light CPU workload, leading to undesirable cache misses and power penalties.

Innovation Solution

Implementing a dynamic cache extension system that uses a cache controller to determine if a task is limited by cache size or performance thresholds, allowing the extension of a first processor cluster's cache with a portion of a second processor cluster's cache, thereby optimizing task scheduling and power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the scheduler migrates tasks from a Little cluster to a Big cluster, then performance is improved, but power consumption increases

Engineering Contradiction:
ImproveperformanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic cache extension where the Little cluster's L2 cache can be dynamically extended by borrowing capacity from the Big cluster's L2 cache based on real-time workload characteristics. This dynamic adjustment allows tasks to run on the power-efficient Little cluster while accessing extended cache capacity, avoiding the need to migrate to the power-hungry Big cluster for cache-related performance improvements.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the scheduler keeps tasks in the Little cluster with smaller L2 cache, then power consumption is reduced, but performance suffers

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent merges the cache resources of the Big and Little clusters by allowing the Little cluster to extend its L2 cache capacity using available capacity from the Big cluster's L2 cache. This merging of cache resources enables the Little cluster to handle workloads that require larger cache capacity without migrating tasks to the Big cluster, thus maintaining power efficiency while improving performance.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If the system uses a fixed cache size architecture, then device complexity is reduced, but adaptability to different use cases deteriorates

Engineering Contradiction:
Improvearchitecture complexityVSAvoiduse case optimization
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic cache extension that allows the Little cluster's L2 cache size to vary based on workload requirements. The cache controller monitors workload characteristics and dynamically adjusts the cache extension amount, enabling the system to adapt to different use cases (such as wide memory access patterns) without requiring complex static architecture design for each scenario.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3245587B1Systems and methods for providing dynamic cache extension in a multi-cluster heterogeneous processor architecture
Publication Date: 2020.07.15 QUALCOMM INC
  • EP3245587B1 patent drawingFigure 1
  • EP3245587B1 patent drawingFigure 2
  • EP3245587B1 patent drawingFigure 3

AI summary

A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described: a system includes a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.