Dynamic Cache Layout for Workload-Adaptive Storage Arrays

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Solution Overview

Problem

Existing storage arrays face inefficiencies in managing cache resources due to static allocation strategies that do not adapt to varying input/output (IO) workloads, leading to suboptimal performance and resource utilization.

Innovation Solution

Dynamic adjustment of cache slot allocations in cache segments of global memory based on IO workload characteristics, including type, size, pattern, and sequence, using machine learning techniques to optimize cache layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static cache allocation strategies are used, then device complexity is reduced, but cache performance and resource utilization deteriorate

Engineering Contradiction:
Improvecache management complexityVSAvoidcache performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic cache slot allocation where the storage array continuously monitors IO workload characteristics (read/write ratios, access patterns, data sizes) and automatically adjusts cache segment allocations in real-time. This dynamic adaptation allows the system to optimize cache performance for varying workloads without manual intervention, resolving the contradiction between simplicity and performance.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes allocation parameters (cache slot sizes, segment distributions) based on monitored workload parameters such as read/write ratios, access patterns, and data access frequencies. By adjusting these parameters dynamically, the system optimizes cache utilization for different IO workloads while maintaining manageable complexity through automated parameter tuning.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If static cache allocation strategies are used, then ease of operation is improved, but adaptability to varying workloads deteriorates

Engineering Contradiction:
Improvecache management easeVSAvoidworkload adaptability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The storage array performs self-optimization by automatically monitoring its own IO workload characteristics and adjusting cache allocations without external intervention. The system serves itself by detecting workload patterns, determining optimal cache segment allocations, and implementing changes autonomously, thereby maintaining ease of operation while achieving high adaptability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system incorporates feedback mechanisms where IO workload characteristics (read/write ratios, access patterns, response times) are continuously monitored and used to adjust cache allocations. This closed-loop feedback ensures the cache configuration adapts to varying workloads while the automation maintains operational simplicity.

Inventive Principle:
Principle #23Feedback

3Device complexity

If uniform cache allocation is used, then device complexity is reduced, but loss of energy deteriorates

Engineering Contradiction:
Improvecache allocation complexityVSAvoidenergy efficiency
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent applies local quality by allocating different cache slot sizes to different cache segments based on their specific workload characteristics. Instead of uniform allocation, the system identifies which cache segments handle read-heavy vs. write-heavy workloads and allocates resources accordingly, optimizing energy efficiency by directing cache capacity to where it is most needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system implements partial allocation strategies where cache slots are distributed partially across different segments based on actual workload demands. Rather than allocating full capacity uniformly, the system allocates only the necessary portion of cache to each segment, reducing energy consumption in segments with lower demand while maintaining performance where needed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12423240B2Cache layout optimization
Publication Date: 2025.09.23 DELL PROD LP
  • US12423240B2 patent drawing
  • US12423240B2 patent drawing
  • US12423240B2 patent drawing

AI summary

One or more aspects of the present disclosure relate to cache layout optimization. In embodiments, an input/output (IO) workload is received by a storage array. Further, cache slot allocations are dynamically adjusted for each cache segment of global memory based on one or more characteristics of the IO workload.