Dynamic Cache Line Size Control for Multi-Core Semiconductor Devices
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Solution Overview
Problem
Current semiconductor devices with multiple cores and shared caches lack an effective method to improve access efficiency by dynamically switching cache line sizes, which is essential for optimizing data access in varying memory usage patterns.
Innovation Solution
The semiconductor device incorporates a cache control circuit that collects instruction execution data to calculate execution frequencies for different instruction types and adjusts cache line sizes in each cache based on these frequencies, allowing each core to select an optimal cache line size for improved access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache line size is fixed, then device complexity is reduced, but cache access efficiency deteriorates under varying memory usage patterns
Solution Approach 1:
The cache line size is made dynamically adjustable rather than fixed. The cache control circuit receives instructions to switch between different cache line sizes (first cache line size and second cache line size) based on the type of memory access requested, allowing the system to adapt to varying memory usage patterns and improve cache access efficiency
Solution Approach 2:
The cache line size parameter is changed based on the type of memory access instruction. The cache control circuit identifies whether a access is a global access or local access and switches the cache line size accordingly, optimizing cache performance for different access patterns without requiring complex structural changes
2Productivity
If cache line size is increased, then data transfer efficiency is improved, but cache memory usage efficiency deteriorates for scattered data access
Solution Approach 1:
The cache line size is dynamically switched between a first cache line size for global accesses and a second cache line size for local accesses. This dynamic adjustment allows the system to use larger cache line sizes only when beneficial for data transfer efficiency, while using smaller cache line sizes for scattered data access patterns to maintain cache memory usage efficiency
3Loss of energy
If cache line size is decreased, then cache memory usage efficiency is improved, but data transfer efficiency deteriorates for sequential access patterns
Solution Approach 1:
The cache line size parameter is switched based on the access pattern. For local accesses where data is accessed sequentially or in a localized pattern, a second cache line size is used to improve data transfer efficiency. For global accesses with scattered data patterns, a first cache line size is used to maintain cache memory usage efficiency
Data Source
AI summary
A semiconductor device includes a plurality of cores, each including an instruction execution circuit and a first cache, and a second cache shared by the plurality of cores. In each of the cores, a number of completed instructions for each type of the instructions executed by the instruction execution circuit are counted, and an execution frequency for each type of instructions are calculated. Based on the execution frequencies, a cache line size preferable for use in the first cache in the core is selected. Based on the selected preferable cache line sizes for the cores, a cache line size used in the first caches and the second cache is determined.