Dynamic Cache Line Size Adjustment for SSD L2P Management
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Solution Overview
Problem
Current memory devices face challenges in efficiently managing cache data when the Unified Memory (UM) of a host is either unusable or has a limited size, as they struggle to balance cache line size and data volume without increasing the cache tag volume.
Innovation Solution
The memory device employs a controller that dynamically adjusts the cache line size of the L2P cache based on the availability of the host's UM, securing the L2P cache in either the RAM or the UM, and enlarging the cache line size when the UM is usable to manage more data without increasing the cache tag volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cache line size is increased to manage more data, then the data volume capacity is improved, but the cache tag volume increases
Solution Approach 1:
The cache line size is made dynamic rather than fixed. The controller selectively sets different cache line sizes (first cache line size or second cache line size) based on the operational context, specifically whether the host memory is being used for caching. This dynamic adjustment allows the system to optimize between data volume capacity and cache tag volume depending on current system conditions.
Solution Approach 2:
The system changes the parameter of cache line size based on the usage state of host memory. When host memory is available, a second cache line size is used; when not available, a first cache line size is used. This parameter change enables the system to adapt to different operational scenarios and resolve the contradiction between managing more data and maintaining small cache tag volume.
2Quantity of substance
If the cache line size is enlarged when UM is usable, then more data can be managed without increasing cache tag volume, but the system complexity increases due to dynamic adjustment
Solution Approach 1:
The controller automatically detects the usage state of host memory and self-adjusts the cache line size without requiring external intervention or complex management logic. The system monitors whether host memory is being used and autonomously selects the appropriate cache line size, thereby managing more data while keeping the control mechanism relatively simple.
3Productivity
If the L2P cache is secured in host memory, then read operation efficiency is improved, but the system becomes dependent on host memory availability
Solution Approach 1:
The system applies different cache line sizes to different operational contexts. When host memory is available and being used, a larger cache line size is applied to optimize read efficiency. When host memory is not available or not being used, a different cache line size is applied to maintain functionality. This local quality approach allows the system to optimize for read efficiency in favorable conditions while remaining adaptable to unfavorable conditions.
Data Source
AI summary
According to one embodiment, a part of first information stored in a nonvolatile second memory is cached in a volatile third memory with a first cache line size in a case where a first memory included in a host is not used. A part of the first information is cached in the first memory with a second cache line size in a case where the first memory is used. The second cache line size is larger than the first cache line size.