Dynamic Cache Line Sizing for Memory Efficiency
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Solution Overview
Problem
Sector caches have higher cache miss ratios and inefficient use of cache capacity due to evicting sectors before all subsectors are loaded, leading to unused space and reduced performance.
Innovation Solution
A storage system with data storage lines of different sizes, where a controller dynamically allocates cache lines of varying sizes based on data type, optimizing cache miss rates and memory efficiency by combining smaller cache lines for non-RT textures and larger cache lines for RT textures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a sector cache is used to reduce bus traffic and cache miss handling time, then cache miss handling time is reduced, but cache capacity utilization deteriorates due to evicting sectors before all subsectors are loaded
Solution Approach 1:
The patent segments the cache into multiple banks, each bank containing multiple sets of cache lines. This segmentation allows different cache lines within the same bank to have different sizes, enabling fine-grained control over cache capacity allocation while maintaining the ability to evict individual cache lines rather than entire sectors, thus improving cache capacity utilization without sacrificing cache miss handling time.
Solution Approach 2:
The patent implements dynamic cache line sizing where each cache line can be configured with a specific size based on the data being stored. This dynamic adjustment allows the cache to optimize between storing more data (larger cache lines) or fewer data types (smaller cache lines) in real-time, resolving the contradiction between reducing cache miss handling time and improving cache capacity utilization.
2Device complexity
If large cache blocks are used to reduce the number of tag bits, then tag storage requirements are reduced, but every cache miss requires fetching a large block in its entirety, increasing bus traffic
Solution Approach 1:
The patent divides the cache into multiple banks with multiple sets, allowing the system to use smaller cache line sizes within each set while maintaining overall cache capacity. This segmentation enables selective fetching of only the necessary cache lines on a cache miss, reducing bus traffic without requiring excessively large cache blocks, thus resolving the contradiction between tag storage requirements and bus traffic.
Solution Approach 2:
Different cache lines within the same bank can have different sizes optimized for their specific data types. This local quality approach allows the system to use smaller cache lines for data types that don't require large blocks, reducing the amount of data fetched on cache misses and thereby reducing bus traffic while maintaining efficient tag storage.
Data Source
AI summary
A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each associated with one data storage line allocated in the data storage device, and a controller. The controller sets a first number of address tags and configures a first number of data storage lines to serve as a first data storage line with a first data storage line size, and sets a second number of address tags and configures a second number of data storage lines to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.