Dynamic Cache Memory Modulation for Cloud I/O Bottlenecks

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Solution Overview

Problem

Cloud computing systems face challenges in improving Input/Output (I/O) performance due to limited cache memory, which leads to slower access times for 'cold' data relegated to non-volatile storage, and existing solutions rely on expensive solid-state disks (SSDs) to enhance cache capacity.

Innovation Solution

A method to dynamically modulate cloud cache memory by migrating data from non-volatile memory to volatile cache memory, partitioning it into optimal object sizes for throughput, and analyzing I/O performance to retain 'hot' data in volatile memory while moving 'cold' data to non-volatile storage, thereby optimizing read/write performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cache memory size is increased to improve I/O performance, then IOPS increases, but system cost increases due to expensive volatile cache memory

Engineering Contradiction:
ImproveI/O performanceVSAvoidcache memory capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent combines volatile cache memory and non-volatile storage into a unified cache hierarchy, allowing the system to leverage both fast volatile memory and大容量 non-volatile storage together as an integrated cache system, thereby improving I/O performance without linearly increasing costs

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system dynamically changes the accessibility parameters of cached objects by migrating them between volatile and non-volatile storage based on access patterns, effectively adjusting the performance characteristics of the cache to match actual workload requirements rather than providing uniform high-speed access to all data

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If non-volatile storage is used to expand cache capacity, then cache size increases, but access speed decreases

Engineering Contradiction:
Improvecache capacityVSAvoidaccess time
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent segments the cache into different tiers with volatile memory holding frequently accessed objects and non-volatile storage holding less frequently accessed objects, allowing the system to maintain large cache capacity while ensuring that hot data remains easily accessible

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system introduces a caching layer with intelligent migration capabilities that acts as an intermediary between volatile and non-volatile storage, managing data movement between the two media based on access patterns to hide the speed difference

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If volatile cache memory is used to improve access speed, then I/O performance increases, but system cost increases

Engineering Contradiction:
Improveaccess speedVSAvoidvolatile cache capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent implements dynamic cache management where the boundary between volatile and non-volatile cache is not fixed but adapts based on object access patterns, allowing the system to optimize the use of expensive volatile memory by keeping only the most frequently accessed data in it

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10140030B2Dynamic modulation of cache memory
Publication Date: 2018.11.27 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10140030B2 patent drawing
  • US10140030B2 patent drawing
  • US10140030B2 patent drawing

AI summary

One or more processors migrate an amount of cloud data from a non-volatile memory to a volatile cache memory. One or more processors partition the amount of cloud data into a plurality of objects of a size that allow for a satisfactory read/write throughput performance. One or more processors analyze the plurality of objects for input/output performance over a time period. One or more processors migrate a first portion of the plurality of objects back to the non-volatile memory, wherein the first portion of the plurality of objects exhibit a first input/output performance lower than a first threshold value.