Dynamic Cache Partitioning for Low Power State Energy Efficiency
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Solution Overview
Problem
Modern processors face inefficiencies in power management when transitioning to low power states, as flushing cache memory to save energy results in performance and power penalties upon wake-up, especially when the core needs to re-fetch data from system memory.
Innovation Solution
Dynamically determining and maintaining an optimal portion of the last level cache in a powered state based on workload memory boundedness, allowing context retention and reducing cache flush energy costs while entering package low power states, using a power management mechanism that adjusts cache size according to memory dependency ratios and thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If cache memory is flushed and powered down to save energy, then power consumption is reduced, but performance deteriorates due to data fetch penalties upon wake-up
Solution Approach 1:
The cache memory is divided into multiple ways that can be independently controlled. Instead of flushing and powering down the entire cache, the patent selectively powers down only the portions of cache that are not needed, while maintaining power to other cache ways that may be required upon wake-up. This segmentation allows the system to achieve power savings while preserving performance-critical data in retained cache portions.
2Loss of energy
If entire cache memory is powered down to maximize energy savings, then power consumption is minimized, but context loss occurs requiring re-fetch from system memory
Solution Approach 1:
Different portions of the cache memory are treated differently based on their usage patterns and importance. The patent identifies which cache ways are most likely to be needed upon wake-up and maintains power to those specific local regions, while allowing other regions to be powered down. This local quality approach preserves critical context information while achieving significant energy savings.
3Use of energy by moving object
If cache size is reduced to minimize power consumption, then energy efficiency improves, but availability of needed data decreases
Solution Approach 1:
The patent implements dynamic control of cache size by adjusting the number of active cache ways based on system state and workload characteristics. When entering low-power states, the system dynamically reduces the active cache portion to minimize power consumption. Upon wake-up, the system can dynamically expand or reconfigure the active cache based on data availability needs, ensuring reliable data access while maintaining energy efficiency during idle periods.
Data Source
AI summary
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.