Dynamic Cache Allocation for SLC Ping-Pong Reduction
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Solution Overview
Problem
Existing cache allocation methods in electronic devices suffer from low cache hit rates and increased power consumption due to cache ping-pong effects, particularly in system-level caches like SLC, which are smaller than main memory and experience frequent data flushing and retrieval, leading to inefficient data access.
Innovation Solution
A dynamic cache allocation method that determines candidate memory buffers based on usage frequency, size, and refresh parameters to dynamically lock and flush cache areas, optimizing cache usage and reducing ping-pong effects by selecting buffers with high refresh frequencies for caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cache allocation is performed without considering usage frequency, then cache allocation is simple, but cache hit rate is low
Solution Approach 1:
The patent changes the parameter of cache allocation from static to dynamic by introducing usage frequency as a variable. The system monitors and calculates usage frequency of memory buffers and adjusts cache allocation accordingly, transforming the allocation strategy from a fixed approach to an adaptive one that responds to actual access patterns.
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors memory buffer usage frequency and uses this information to adjust cache allocation decisions. The usage frequency data feeds back into the allocation algorithm, creating a closed-loop system that learns from past access patterns and optimizes future allocations.
2Measurement precision
If cache allocation is performed frequently to adapt to usage patterns, then cache hit rate improves, but power consumption increases
Solution Approach 1:
The patent introduces dynamic adaptation to cache allocation by using usage frequency as a decision criterion. Instead of static allocation or overly frequent re-allocation, the system dynamically adjusts cache locking based on actual buffer access patterns, allocating cache resources more intelligently to reduce unnecessary operations.
Solution Approach 2:
The patent applies partial action by selectively locking only those memory buffers that meet the usage frequency threshold, rather than locking all buffers or performing full cache re-allocation. This partial approach reduces the overall system overhead and power consumption while still capturing the benefits of adaptive caching for frequently accessed data.
3Measurement precision
If system-level cache size is increased to reduce flushing, then cache hit rate improves, but device size and cost increase
Solution Approach 1:
The patent changes the allocation strategy parameter from static to dynamic based on usage frequency. By monitoring how often memory buffers are accessed and adjusting cache allocation accordingly, the system maximizes the utility of the available cache size, ensuring that frequently accessed data resides in cache while minimizing the need for larger cache capacity.
4Reliability
If memory buffer data is frequently flushed to main memory, then memory consistency is maintained, but access speed decreases
Solution Approach 1:
The patent applies local quality by differentiating between memory buffers based on their usage frequency characteristics. Frequently accessed buffers receive special treatment through cache locking, while less frequently accessed buffers follow the standard flush-to-main-memory protocol. This localized optimization maintains memory consistency for all buffers while speeding up access for the critical subset.
Data Source
AI summary
A cache allocation method includes: determining multiple candidate memory buffers; determining a target memory buffer among the multiple candidate memory buffers whose attribute information meets a preset requirement, wherein the attribute information is related to a usage frequency of corresponding candidate memory buffer; and locking a corresponding cache area within a cache for the target memory buffer to cache data in the target memory buffer.