Dynamic Cache Way Allocation for Shared Processor Systems

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Solution Overview

Problem

Conventional cache control apparatuses for shared set-associative cache memory systems face inefficiencies in allocating cache capacity, leading to insufficient capacity for high-priority processes, idle resource underutilization, and access delays due to unmanaged cache collisions between processors.

Innovation Solution

A cache control apparatus that dynamically allocates idle cache ways to tasks based on processor priority and availability, preventing collisions by grouping ways and allocating unallocated ways to corresponding processors, ensuring even distribution and utilization of cache resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If cache memory is shared by multiple processors, then system resource utilization is improved, but access delays occur due to cache collisions between processors

Engineering Contradiction:
Improvecache sharing capabilityVSAvoidaccess delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The cache memory is divided into multiple independent groups, where each group can be independently allocated to different processors. This segmentation prevents cache collisions by ensuring that processors access different cache groups simultaneously, thereby reducing access delays while maintaining shared cache benefits

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache allocation is made dynamic through a cache allocation control unit that can reallocate cache groups based on processor priority and current cache usage status. High-priority processors can be dynamically assigned additional cache groups when idle groups are available, optimizing performance while reducing access delays

Inventive Principle:
Principle #15Dynamics

2Productivity

If cache capacity is allocated based on processor priority, then system performance is improved, but idle cache resources remain underutilized

Engineering Contradiction:
Improvesystem performanceVSAvoidcache resource underutilization
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The cache allocation control unit continuously monitors the usage status of cache groups and processor priorities, using this feedback information to dynamically reallocate idle cache groups to processors that need them. This feedback mechanism ensures that cache resources are fully utilized while maintaining performance optimization for high-priority processors

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

When processors complete their tasks or lower their priority, their allocated cache groups are recovered and made available for reallocation to other processors. This prevents cache resource underutilization by ensuring that idle cache groups are continuously reused by other active processors

Inventive Principle:
Principle #34Discarding and recovering

3Ease of operation

If fixed cache allocation is used, then cache management is simplified, but insufficient cache capacity occurs for high-priority processes

Engineering Contradiction:
Improvecache management simplicityVSAvoidhigh-priority process performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system transitions from fixed to dynamic cache allocation, where the cache allocation control unit automatically adjusts cache group assignments based on real-time processor priority information. This dynamic approach ensures that high-priority processes receive sufficient cache capacity without requiring complex manual management

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The cache allocation control unit automatically manages cache group allocation and reallocation based on processor priority and cache usage status, eliminating the need for manual intervention. This self-service mechanism maintains simplicity while optimizing cache capacity distribution to high-priority processes

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8868835B2Cache control apparatus, and cache control method
Publication Date: 2014.10.21 SOCIONEXT INC
  • US8868835B2 patent drawing
  • US8868835B2 patent drawing
  • US8868835B2 patent drawing

AI summary

A cache control apparatus according to the present invention includes a cache allocation control unit which allocates each of a plurality of ways included in a cache memory to one or more of tasks to be executed by a plurality of processors. In the case where a group of ways includes an unallocated way that is not allocated to any of the tasks and a way allocated to one or more of the tasks which is to be executed by one of the processors, the cache allocation control unit allocates the unallocated way included in the group to the one or more of the tasks to be executed by the one of the processors.