Dynamic Cache Way Scaling for Voltage-Induced Memory Failures
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Solution Overview
Problem
The fixed minimum supply voltage (Vmin) in data processing systems limits memory functionality and efficiency, as it is set higher than the voltage at which most memories can operate, leading to loss of functionality and efficiency at lower supply voltages, where only a small fraction of memory bits fail, causing non-functional sections to retain data but not allow reliable access.
Innovation Solution
A multiple way cache is implemented, where the number of functional cache ways is dynamically adjusted based on changes in operating voltage and temperature, allowing for different voltage levels to enable or disable cache ways, thereby scaling memory size and maintaining data integrity at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed minimum supply voltage (Vmin) is set with a guard band to prevent voltage sensitive bits from failing, then memory reliability is improved, but memory functionality and efficiency deteriorate at lower supply voltages
Solution Approach 1:
The patent implements dynamic voltage-based memory size scaling where the operational memory size is adjusted in real-time based on the supply voltage level. At lower voltages, only a subset of memory bits are activated that are guaranteed to function reliably, while at higher voltages, the full memory capacity becomes accessible. This dynamic adaptation resolves the contradiction by making memory functionality dependent on voltage conditions rather than using a fixed conservative Vmin setting.
Solution Approach 2:
The system changes the operational parameter of memory size based on supply voltage levels. By monitoring the actual supply voltage and dynamically adjusting the number of operational memory bits accordingly, the system optimizes both reliability and functionality. When voltage is high, more bits operate; when voltage is low, fewer bits operate but with higher confidence of reliability.
2Use of energy by moving object
If the supply voltage is reduced to increase efficiency, then energy consumption is improved, but memory functionality deteriorates due to voltage sensitive bits failing
Solution Approach 1:
The patent applies partial action by activating only the necessary subset of memory bits that can reliably operate at the current supply voltage level. Instead of attempting to use the full memory capacity at all voltage levels, the system selectively enables only those bits that will function correctly, accepting that some memory capacity remains unused at lower voltages but ensuring that the used portion operates reliably.
3Reliability
If a fixed Vmin level is selected higher than the supply voltage level at which most memories can operate, then voltage sensitive bits are protected from failing, but loss of functionality and efficiency occurs in memory usage
Solution Approach 1:
The system dynamically adjusts the effective memory size based on actual supply voltage conditions rather than using a fixed conservative Vmin level. This allows the memory subsystem to efficiently utilize available capacity at each voltage level while maintaining reliability for the activated portion, thereby improving overall memory usage productivity compared to a fixed conservative approach.
Data Source
AI summary
A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.