Dynamic Inclusive Non-Inclusive Caching Policy Selection
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Solution Overview
Problem
Current caching policies are static, failing to dynamically adjust between inclusive and non-inclusive modes, leading to suboptimal performance and increased overhead in computing systems with varying numbers of active processor cores, which affects computing speed and power consumption.
Innovation Solution
A dynamic caching policy selection mechanism using machine learning to determine the best caching policy based on telemetry data, switching between inclusive and non-inclusive policies during runtime, with a logistic regression model predicting the optimal policy based on core activity levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a static caching policy is used, then the system is simple to implement, but the performance is suboptimal when the number of active processor cores varies
Solution Approach 1:
The patent implements a dynamic caching policy that automatically switches between inclusive and non-inclusive modes based on the number of active processor cores. A core activity monitor detects changes in active core count, and a policy selector switches the caching policy accordingly, allowing the system to adapt to varying workload conditions and optimize performance without manual intervention
Solution Approach 2:
The patent changes the inclusivity parameter of the caching policy based on system conditions. When the number of active cores exceeds a threshold, the system switches from inclusive to non-inclusive caching mode, and vice versa. This parameter change allows the system to optimize for different scenarios: inclusive mode for fewer cores (reducing duplicate data) and non-inclusive mode for more cores (reducing writeback operations)
2Reliability
If an inclusive caching policy is used, then data correctness is maintained, but clean writeback operations increase leading to higher overhead
Solution Approach 1:
The patent dynamically switches between inclusive and non-inclusive caching policies based on the number of active processor cores. When many cores are active, the system uses non-inclusive mode to minimize clean writeback operations and reduce cache coherence overhead, while maintaining data correctness through appropriate invalidation protocols. When fewer cores are active, it switches to inclusive mode to eliminate duplicate data and reduce memory traffic
Solution Approach 2:
The patent changes the caching policy parameter (inclusive vs. non-inclusive) based on system conditions. Non-inclusive mode is selected when active core count exceeds a threshold, reducing writeback overhead by allowing lower-level caches to evict clean lines without requiring upper-level cache updates. Inclusive mode is selected when active core count is below the threshold, ensuring data correctness by maintaining copies in upper-level caches
3Device complexity
If a non-inclusive caching policy is used, then clean writeback operations are reduced, but power consumption increases due to increased traffic between cache levels
Solution Approach 1:
The patent implements a dynamic policy selection mechanism that monitors active core count and switches between inclusive and non-inclusive caching modes. When the number of active cores is low, the system uses inclusive mode to reduce memory traffic and power consumption by eliminating duplicate data. When active core count increases, it transitions to non-inclusive mode to reduce writeback operations, accepting the trade-off in power consumption as the system utilizes more processing resources
Solution Approach 2:
The patent changes the caching policy parameter based on active core count threshold. The system selects non-inclusive mode when active cores exceed the threshold, reducing writeback operations despite increased power consumption from cache level traffic. When active cores are below the threshold, it selects inclusive mode to minimize power consumption by reducing overall memory traffic and eliminating redundant data storage
Data Source
AI summary
Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.