Dynamic Command Address Inversion for DRAM Power Reduction
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Solution Overview
Problem
Conventional memory devices face challenges in maintaining signal integrity and reducing power consumption as memory speeds increase, particularly due to impedance mismatches and the power draw associated with on-die termination (ODT) in dynamic random access memory (DRAM) systems.
Innovation Solution
The implementation of dynamic command/address inversion (CAI) in memory systems, where the decision to invert command/address values is made dynamically based on the true CA value for each operation, helps reduce power consumption while maintaining signal integrity. This is achieved by evaluating the number of 1s and 0s in the command/address values and determining whether to use the true or inverted values for transmission to memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die termination (ODT) is used to maintain signal integrity at high memory speeds, then signal integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the command/address inversion state changeable over time. A training phase determines the optimal inversion state (inverted or non-inverted) for each memory device, and this state is dynamically applied during operation. This dynamic adaptation allows the system to optimize power consumption while maintaining signal integrity, as the inversion state can be selected to minimize ODT power draw without compromising reliability.
Solution Approach 2:
The patent changes the parameter of command/address signal inversion state to resolve the contradiction. By toggling the inversion state between inverted and non-inverted configurations based on training results, the system alters the electrical characteristics of the command/address buses. This parameter change enables optimization of the balance between 0s and 1s transmitted, thereby reducing ODT power consumption while preserving signal integrity through trained optimization.
2Use of energy by moving object
If command/address values are transmitted with more 0s than 1s (or vice versa), then power consumption is reduced, but signal balance and integrity may be compromised
Solution Approach 1:
The patent applies preliminary action through a training phase that occurs before normal operation. During this training phase, the system evaluates which inversion state (inverted or non-inverted) produces a more balanced distribution of 0s and 1s on the command/address buses. This preliminary optimization determines the inversion state that will minimize ODT power consumption while maintaining signal integrity, and this predetermined state is then applied during subsequent operational phases.
Solution Approach 2:
The patent uses feedback mechanisms where the training phase evaluates the actual signal characteristics and power consumption effects of different inversion states. Based on this feedback from the training phase, the system selects the optimal inversion state that balances power consumption and signal integrity. This feedback loop ensures that the chosen inversion state truly optimizes the trade-off between reducing power draw and maintaining reliable signal transmission.
Data Source
AI summary
Disclosed are methods, systems, and apparatuses for semiconductor memory devices (e.g., dynamic random access memory (DRAM)) that include a command/address inversion (CAI) input signal indicating whether command/address inputs to the memory devices are inverted. The CAI input signal may be generated by a memory controller, a registering clock driver (RCD), or other component coupled to the memory devices, and the component may generate the CAI input signal differently for the different memory devices to which the component is coupled. As described herein, the component may dynamically generate the CAI input signal based on the values of the command/address inputs so as to reduce power consumption by the memory devices while retaining signal integrity.