Dynamic Cascode Biasing in Comparators for Single-Slope ADC Noise
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Solution Overview
Problem
Column parallel single slope ADCs face challenges in reducing noise and signal offsets due to coupling between comparators, particularly when dealing with non-constant input signals and wide full-scale ranges, making it difficult to select an optimal cascode bias voltage.
Innovation Solution
A cascoded comparator with dynamic biasing is introduced, where a cascode bias generator generates a biasing signal that tracks the input ramp signal with a fixed offset, applied to cascode transistors to maintain consistent operating characteristics and prevent signal coupling, ensuring accurate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cascode transistors are added to the comparator input circuit to eliminate coupling between comparators, then noise and signal offsets are reduced, but it becomes difficult to select an optimal cascode bias voltage due to non-constant input signals and wide full scale range
Solution Approach 1:
The patent implements dynamic biasing where the cascode bias voltage is no longer fixed but varies dynamically to track the input signal level. The bias generator circuit produces a bias voltage that automatically adjusts according to the instantaneous input signal, ensuring optimal operating point for the cascode transistors across the entire wide input range. This resolves the contradiction by making the bias voltage adaptive rather than static, eliminating the difficulty of selecting a single optimal bias voltage for all input conditions.
Solution Approach 2:
The patent employs feedback mechanisms where the input signal is fed back to the bias generator circuit, which then generates the appropriate cascode bias voltage. This feedback loop ensures that the bias voltage automatically follows the input signal variations, maintaining optimal transistor operation without requiring manual adjustment or complex selection processes. The feedback approach directly addresses the ease of operation issue while preserving the noise reduction benefits.
2Measurement precision
If cascode transistors are added to clamp drain voltage and prevent switching signal coupling, then conversion accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces a bias generator circuit as an intermediary component that mediates between the input signal and the cascode transistors. This intermediary generates the appropriate bias voltages dynamically, allowing the cascode transistors to function effectively without requiring complex control logic or additional switching elements. The bias generator acts as a smart intermediary that simplifies the overall circuit architecture while maintaining high conversion accuracy through adaptive biasing.
Solution Approach 2:
The patent changes the operating parameters of the cascode transistors dynamically by varying their bias voltages according to the input signal level. Instead of using complex circuit topologies or additional components, the solution modifies the voltage parameters of existing transistors to achieve optimal performance across different operating conditions. This parameter-based approach increases conversion accuracy while minimizing the increase in device complexity.
Data Source
AI summary
Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.