Dynamic Central Cache Memory Resource Allocation

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Solution Overview

Problem

Current memory storage systems, particularly managedNAND types like eMMC and SSD, face inefficiencies due to insufficient embedded memory resources, leading to delays and wear-out issues when handling runtime data, especially in networked devices with limited resources.

Innovation Solution

Implementing a central cache module that dynamically allocates and manages memory resources across multiple memory modules, using pre-set or run-time reservations based on device IDs, class IDs, and memory types, to optimize resource utilization and reduce reliance on slower non-volatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory resources are reserved statically for each memory module, then reliability is improved, but adaptability deteriorates

Engineering Contradiction:
Improvememory operation reliabilityVSAvoidresource allocation flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic resource allocation mechanism where the cache module can switch between static reservation modes and dynamic allocation modes. The system determines resource allocation based on real-time operational states, allowing it to adapt to different scenarios while maintaining reliability through structured allocation protocols.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The cache module serves multiple functions: it acts as both a reserved resource for specific memory modules and a dynamic allocation pool for other modules. This multi-functionality allows the system to maintain reliability for critical operations while providing adaptability for varying workload demands.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If embedded memory resources are increased, then system performance is improved, but device complexity increases

Engineering Contradiction:
Improvememory operation speedVSAvoidmemory architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a cache module as an intermediary between memory modules and the host device. This cache module manages resource allocation and operations, reducing the complexity burden on individual memory modules while improving overall system performance through centralized intelligent management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The memory system is segmented into distinct functional components: memory modules, cache module, and host device. Each segment has specialized responsibilities, with the cache module handling resource management tasks. This segmentation improves performance by optimizing each component's function while managing complexity through clear functional boundaries.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If dynamic resource allocation is implemented, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The cache module implements self-service mechanisms for resource allocation, using predefined criteria and automated decision-making algorithms to determine resource distribution. This reduces the need for complex external control mechanisms while maintaining high adaptability to different operational scenarios.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system dynamically changes allocation parameters based on operational conditions, such as memory module status, workload demands, and performance metrics. By adjusting these parameters through standardized protocols, the system achieves adaptability without requiring fundamentally complex control architectures.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9116820B2Dynamic central cache memory
Publication Date: 2015.08.25 MEMORY TECHNOLOGIES LLC
  • US9116820B2 patent drawing
  • US9116820B2 patent drawing
  • US9116820B2 patent drawing

AI summary

The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.