Dynamic Charge Pump Circuit for PLL Locking Speed and Jitter Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase locked loop (PLL) circuits face a trade-off between reducing lock-in time and minimizing phase jitter noise bandwidth, as increasing the natural frequency to speed up locking introduces more jitter into the system.
Innovation Solution
A charge pump circuit with dynamic current biasing that adjusts the charge pump current to increase the natural frequency for faster locking and then decreases it to minimize jitter noise bandwidth after locking, using a configuration of PMOS and NMOS transistors, operational amplifiers, and capacitors to control current flow and voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the natural frequency of the PLL circuit is increased to reduce lock-in time, then the locking speed is improved, but the phase jitter noise bandwidth increases introducing more jitter into the system
Solution Approach 1:
The charge pump current is made dynamically adjustable rather than fixed. The circuit transitions from a static current source to a dynamic current source that can be modulated in response to PLL locking state, enabling the system to optimize performance at different operational phases
Solution Approach 2:
The charge pump current parameter is changed dynamically based on PLL locking state. During initial acquisition, higher current is used to reduce lock-in time; after locking, current is reduced to minimize phase jitter noise. This parameter modulation resolves the contradiction between speed and noise
2Productivity
If the charge pump current is increased to increase the natural frequency, then the lock-in time is reduced, but more current is consumed and jitter noise is introduced
Solution Approach 1:
The charge pump current is applied in periodic phases: high current during initial locking acquisition, then switched to low current after locking is achieved. This periodic modulation of current enables fast locking when needed while conserving energy during the sustained locked state
Solution Approach 2:
The charge pump current parameter is dynamically adjusted based on locking state, transitioning from high current (fast locking) to low current (energy saving). This parameter change resolves the contradiction between productivity and energy consumption
3Reliability
If the charge pump current is increased to reduce lock-in time, then the locking performance is improved, but phase jitter noise bandwidth increases
Solution Approach 1:
The charge pump circuit transitions from a static current source to a dynamic current source that responds to PLL locking state. This dynamic behavior enables the circuit to provide high current for reliable locking acquisition, then reduce current to minimize noise bandwidth during stable operation
Solution Approach 2:
The charge pump current parameter is modulated based on locking state to resolve the contradiction between reliability and noise. High current ensures reliable fast locking; low current minimizes phase jitter noise bandwidth after locking
Data Source
AI summary
A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.