Dynamic Charge Pump Frequency Control for Display Power Efficiency
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Solution Overview
Problem
Current charge pump circuits in display devices consume excess power due to high switching frequency and capacitance requirements, particularly in voltage holding times, which increases power consumption and reduces efficiency.
Innovation Solution
A power circuit with a timing controller and level detecting unit that adjusts the switching frequency and capacitance of the charge pump in real-time, increasing frequency and capacitance during voltage conversion times for rapid charging and reducing them during voltage holding times to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the charge pump circuit uses high switching frequency and high multiple to rapidly raise voltage during voltage conversion time, then the response speed of the display device is improved, but the power consumption increases excessively
Solution Approach 1:
The patent applies dynamics by making the switching frequency and capacitance of the charge pump adjustable rather than fixed. The control circuit dynamically changes the switching frequency and capacitance values based on the operating state (voltage conversion time vs. voltage holding time), allowing the system to optimize between response speed and power consumption in different phases of operation
Solution Approach 2:
The patent changes the parameters of the charge pump circuit by adjusting the switching frequency and capacitance values. During voltage conversion time, higher frequency and capacitance are used to achieve rapid voltage rise, while during voltage holding time, lower frequency and capacitance are used to reduce power consumption, thus resolving the contradiction between speed and energy usage
2Reliability
If the charge pump circuit maintains high switching frequency during voltage holding time to ensure voltage stability, then the reliability is improved, but the power consumption increases unnecessarily
Solution Approach 1:
The patent applies partial action by providing just enough switching activity to maintain voltage stability during holding time, rather than continuously operating at maximum frequency. The control circuit reduces the switching frequency and capacitance to minimum levels required for stability, avoiding excessive power consumption while maintaining adequate voltage regulation
Solution Approach 2:
The patent uses periodic action by implementing intermittent switching during voltage holding time. Instead of continuous high-frequency switching, the charge pump operates at reduced frequency with longer intervals between switching cycles, which is sufficient to maintain voltage stability while significantly reducing power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the response speed of display devices during voltage conversion while minimizing power consumption by optimizing switching frequency and capacitance, thus achieving efficient power management.
Implementation Method 1
the voltage source and the charging capacitor are connected in parallel using the plurality of switches for charging the charging capacitor to a voltage level
Implementation Method 2
the charging capacitor is connected in series with the output capacitor. After repeated for a plurality of cycles, the voltage across the output capacitor will be raised to a voltage level much higher than the original voltage source
Data Source
AI summary
The present invention relates to a power circuit of displaying device, which comprises a timing controller, a control circuit, and a charge pump (single or multiple stages). The timing controller outputs a timing control signal to the control circuit. The control circuit outputs a clock signal or a capacitance adjusting signal according to the timing control signal. The charge pump receives the input voltage and outputs an output voltage according to the clock signal or the capacitance adjusting signal. The output voltage is provided to the scan driver for generating a plurality of scan driving signals. Accordingly, by increasing the rise rate of the output voltage of the charge pump in the voltage conversion time and reducing the rise rate of the output voltage close to the voltage holding time, the present invention can achieve the effect of reducing the power consumption.