Dynamic Circuit Partitioning for IC Fault Diagnosis
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Solution Overview
Problem
Traditional yield learning methods for IC manufacturing, such as inline inspection and statistical volume diagnosis, become less effective as circuit feature sizes shrink and design complexity increases, leading to increased computational resource requirements and diagnosis time, with modern workstations struggling to efficiently handle large circuit designs due to memory limitations and processor idle time.
Innovation Solution
Dynamic circuit design partitioning extracts sub-circuits based on failure information, combining fan-in cones of failing and passing observation points, utilizing clock and layout information to reduce sub-circuit size, allowing for parallel diagnosis on multiple computers, thereby improving resource utilization and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the circuit design size increases to handle more complex IC designs, then the diagnostic capability improves, but the memory requirements and diagnosis time increase significantly
Solution Approach 1:
The patent divides the large circuit design into multiple smaller sub-circuits or partitions based on the failure information. Instead of loading the entire circuit into memory, only the relevant sub-circuits containing failing observation points are extracted and analyzed. This segmentation allows complex IC designs to be diagnosed using limited memory resources while maintaining diagnostic capability.
2Productivity
If more processors are added to increase diagnosis speed, then the diagnosis throughput improves, but the resource utilization efficiency decreases due to memory bottlenecks
Solution Approach 1:
By segmenting the circuit into smaller sub-circuits, the patent enables multiple sub-circuits to be loaded into memory simultaneously, allowing multiple processors to work in parallel without memory conflicts. This increases diagnosis throughput while maintaining high processor utilization efficiency.
Solution Approach 2:
The patent performs preliminary extraction of sub-circuits based on failure information before the actual diagnosis process. This preliminary action prepares the data in a format that can be efficiently processed by multiple processors in parallel, reducing idle time and improving overall throughput.
3Measurement precision
If the entire circuit design is analyzed for each failing device, then the diagnosis accuracy is maintained, but the processing time increases continuously with design size
Solution Approach 1:
The patent extracts only the relevant sub-circuits containing failing observation points from the entire circuit design. By taking out and analyzing only these critical portions, the diagnosis maintains accuracy for the failing devices while significantly reducing processing time compared to analyzing the complete circuit design.
Data Source
AI summary
Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.