Dynamic Maximal Clique Enumeration with FPGA-HBM Pipelining

The patent segments the incremental maximal clique enumeration process into three distinct pipeline stages: (1) edge change processing that updates the adjacency matrix, (2) candidate clique reconstruction that identifies affected cliques, and (3) maximal clique update that computes the final result. Each stage operates independently and can be processed in parallel, enabling efficient utilization of FPGA hardware resources and significantly improving computing efficiency for large-scale graph data.

The patent implements a dynamic pipeline architecture where data flows continuously through the three computation stages. The system dynamically processes edge additions and deletions in real-time, maintaining up-to-date maximal clique information without requiring full recomputation. This dynamic approach allows the system to adapt to changing graph structures while maintaining high throughput and low latency.

The patent replaces traditional software-based incremental maximal clique enumeration with a hardware-accelerated FPGA implementation. The computation logic is directly mapped to FPGA logic elements, allowing parallel execution of multiple graph operations simultaneously. This substitution of mechanical/computational approach enables full utilization of FPGA's parallel processing capabilities, achieving significant speedup despite increased hardware complexity.

The patent introduces an intermediate adjacency matrix representation that serves as a bridge between the input edge changes and the output maximal clique results. This intermediate structure allows the FPGA to efficiently process edge additions and deletions by maintaining updated neighbor information, enabling fast computation without requiring complex direct mapping from edge changes to clique updates.