Dynamic Clock Frequency Control for At-Speed Circuit Testing
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Solution Overview
Problem
The overhead associated with managing multiple clock domains and frequencies in automatic test pattern generation for circuits is significant, leading to inefficiencies in testing and verification processes.
Innovation Solution
A system and method for dynamically adjusting clock frequencies by analyzing test points and generating control signals to adapt clock signals, utilizing a multiplexer and memory elements to simplify register sizes and enhance stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple clock domains and frequencies are used to test different portions of a DUT, then testing coverage and accuracy are improved, but device complexity and overhead increase significantly
Solution Approach 1:
A single clock domain is used to test multiple portions of the DUT by dynamically reconfiguring the clock frequency. The system can switch between testing different clock domains using the same physical clock resource, eliminating the need for separate clock domains for each test portion. This multi-functional approach reduces logic overhead while maintaining comprehensive testing coverage.
Solution Approach 2:
The clock frequency is made dynamically adjustable during the testing process. Instead of using fixed multiple clock domains, the system can change the clock frequency on-the-fly to match the requirements of different DUT portions being tested. This dynamic reconfiguration allows a single clock domain to serve multiple testing purposes, reducing overall device complexity.
2Adaptability or versatility
If multiple clock domains are supported to cover all test scenarios, then adaptability is improved, but the logic overhead and resource requirements increase
Solution Approach 1:
The system implements a universal clock domain that can be reconfigured to serve multiple testing scenarios. By using a single clock resource that can be dynamically adjusted, the system achieves the adaptability of multiple clock domains without the overhead of implementing and managing multiple separate clock domains. The same clock infrastructure adapts to different testing requirements through frequency reconfiguration.
3Productivity
If dynamic clock frequency adjustment is implemented, then testing efficiency is improved, but control complexity increases
Solution Approach 1:
The system uses feedback mechanisms to automatically determine the appropriate clock frequency for testing different DUT portions. Based on the test requirements and the portion being tested, the system receives feedback information and adjusts the clock frequency accordingly. This automated feedback-based control reduces the manual control complexity while maintaining high testing efficiency.
Data Source
AI summary
Aspects of the subject disclosure may include, for example, monitoring first data to identify a first plurality of test points, analyzing the first plurality of test points to identify the first data as being associated with a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains, and based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal.