Dynamic Clock Control for Bursty Data Processing
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Solution Overview
Problem
Information handling systems face challenges in efficiently managing power consumption due to fixed clock speeds, which can lead to increased power dissipation and thermal issues, especially in processors that require varying levels of performance like graphics processors.
Innovation Solution
A data processor with a clock generator that produces multiple reference clock signals at different rates, synchronized by clock select circuitry and activity logic, allowing for near-instantaneous switching between clock rates based on processing activity, thereby tailoring power consumption to current needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock rate of the reference signal is increased to process data faster, then the data processing speed is improved, but the power dissipation by the integrated circuit increases
Solution Approach 1:
The patent implements dynamic clock rate adjustment by providing multiple reference clock signals at different rates (e.g., 100 MHz, 200 MHz, 400 MHz) and selectively switching between them based on processing load. The clock select circuitry responds to activity indications to dynamically choose the appropriate clock rate, making the system adaptable rather than fixed.
Solution Approach 2:
The system changes the clock rate parameter of the reference clock signal based on processing activity. By varying this critical parameter according to workload demands, the system optimizes the balance between processing speed and power consumption, using higher rates only when necessary.
2Productivity
If a fixed high clock rate is used to ensure performance, then the processing capability is maintained, but power consumption increases and thermal issues arise
Solution Approach 1:
The patent makes the clock rate dynamic rather than fixed, allowing the system to adapt processing capability to actual workload. The clock select circuitry continuously monitors activity indications and adjusts the reference clock rate accordingly, ensuring high performance when needed while reducing power consumption during low-activity periods.
Solution Approach 2:
The system employs periodic monitoring of processing activity through activity logic that generates activity indications at regular intervals. This periodic assessment allows the clock rate to be adjusted in response to changing workload conditions, maintaining performance while minimizing energy loss.
3Use of energy by moving object
If the processor clock rate is reduced to decrease power consumption, then power dissipation is reduced, but the data processing speed decreases
Solution Approach 1:
The system dynamically changes the clock rate parameter based on processing activity levels. When activity is low, the clock rate is reduced to minimize power dissipation; when activity increases, the rate is raised to maintain processing speed, thus adapting to conditions rather than being constrained by either extreme.
Solution Approach 2:
The patent implements a dynamic clocking system where the reference clock rate is continuously adjustable based on workload. This dynamic approach allows the system to optimize the trade-off between power consumption and processing speed in real-time, rather than being locked into a fixed rate.
4Use of energy by moving object
If multiple clock rates are provided and switched based on activity, then power consumption is optimized, but the device complexity increases
Solution Approach 1:
The patent introduces clock select circuitry as an intermediary component that manages the switching between multiple reference clock signals. This dedicated control logic simplifies the overall system architecture by centralizing clock management functions and providing a clear interface between the activity logic and the data processing circuitry.
Solution Approach 2:
The system implements feedback through activity logic that monitors processing activity and generates activity indications that drive clock rate selection. This closed-loop feedback mechanism automates the clock rate adjustment process, reducing the need for complex manual control while optimizing power consumption based on actual workload.
Data Source
AI summary
A variable speed data processor includes a clock generator generating a plurality of clocks at different clock rates. Clock select circuitry synchronously selects one of the clocks as an output clock signal to data processing circuitry, based on a data activity indication. Activity logic generates the data activity indication based at least in part on the existence of data processing activity targeted to the data processing circuitry. When the data processing circuitry experiences bursty data processing activity, the clock rate can shift rapidly between the multiple clock rates, conserving power without substantially diminishing the availability of the data processing circuitry.