Dynamic Clock Control for High-Speed Bus Interfaces
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Solution Overview
Problem
Current multi-drop interface technologies, such as the Improved Inter Integrated Circuit (I3C) Specification, are limited by propagation delay and clock-to-data turnaround delays, restricting bus speed to 12.5 MHz, which is inadequate for high-bandwidth applications.
Innovation Solution
Enabling a slave device to source and control both clock and data lines during communication, allowing the bus to operate at faster clock rates by dynamically handing over clock control from the master to the slave device, potentially exceeding 40 MHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the master device controls the clock line in traditional multi-drop interface, then the system maintains simple control structure, but the bus speed is limited to 12.5 MHz due to propagation delay and clock-to-data turnaround delays
Solution Approach 1:
The patent implements dynamic clock control where the master device can hand off clock line control to slave devices based on communication needs. The system transitions from static master-controlled clocking to dynamic distributed clocking, allowing clock sources to be switched between master and slave devices depending on data transmission requirements, thereby achieving higher bus speeds while maintaining manageable control complexity through structured handoff protocols
Solution Approach 2:
The patent changes the clock frequency parameter from a fixed 12.5 MHz limit to variable frequencies exceeding 40 MHz by enabling slave devices to source clocks. This parameter change is achieved through modifying the clock control mechanism to allow multiple potential clock sources (master or slave) rather than a single fixed source, directly addressing the speed limitation while using established control protocols to manage the change
2Speed
If the master device sources the clock signal, then the clock control is centralized and simple, but propagation delay and clock-to-data turnaround delays limit the communication speed
Solution Approach 1:
The patent applies preliminary action by having the slave device prepare and source the clock signal in advance when it needs to transmit data. Instead of waiting for the master to provide the clock, the slave device proactively generates the clock signal locally, eliminating the propagation delay from master to slave and reducing clock-to-data turnaround time. The master device then hands off clock control to the slave, enabling the slave to immediately use the pre-prepared clock for high-speed data transmission
Solution Approach 2:
The patent introduces a clock control handoff mechanism as an intermediary between the master and slave devices. This handoff protocol acts as a mediator that transfers clock sourcing responsibility from the master to the slave device, enabling the slave to become the local clock source and thereby eliminating the propagation delay associated with master-sourced clocks. The intermediary handoff mechanism manages the transition while maintaining system coordination
Data Source
AI summary
In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.