Dynamic Clock Control Circuit Eliminates Narrow Pulses
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Solution Overview
Problem
Conventional systems with dynamic clock control experience uncertain clocking due to arbitrarily narrow pulses when transitioning between sleep and active modes, leading to potential errors in clocking components.
Innovation Solution
The implementation of circuitry and methods that generate a dynamically controlled clock by combining a running clock with a register data output signal, using a multiplexer to pass control signals and ensure full pulse width during transitions, thereby eliminating abnormally narrow pulses and ensuring smooth clock enable/disable operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clocks are dynamically controlled by disabling and enabling during runtime to reduce power consumption, then power consumption is reduced, but abnormally narrow pulses are generated during transitions causing uncertain clocking
Solution Approach 1:
The patent applies preliminary action by capturing the control signal state in a register before the clock transition occurs. The register holds the enable/disable state information, ensuring that the clock gating logic has stable input data before the actual clock signal is gated, thereby preventing narrow pulse generation during transitions.
Solution Approach 2:
The patent introduces a register as an intermediary element between the control signal source and the clock gating logic. This register acts as a buffer that stabilizes the control signal, preventing direct coupling between the control signal transitions and the clock signal transitions that would otherwise cause abnormally narrow pulses.
2Loss of energy
If clocks are disabled and enabled during sleep mode transitions, then power consumption is reduced, but the last pulse before disabling and first pulse when re-enabling may be arbitrarily narrow
Solution Approach 1:
The register captures the control signal state in advance of the clock transition, ensuring that the enable/disable command is stable and synchronized before affecting the clock signal. This preliminary capture prevents the clock pulse width from becoming arbitrarily narrow during mode transitions.
Solution Approach 2:
The patent employs feedback by using the registered control signal state to regulate the clock gating operation. The registered state feeds back to the clock gating logic, ensuring that clock enable/disable operations are based on stable, previously captured control signals rather than direct, potentially unstable control signal transitions.
3Device complexity
If conventional clock control is used during sleep mode, then circuit simplicity is maintained, but leakage currents are not reduced and power consumption increases
Solution Approach 1:
The register is configured to capture control signals in advance of sleep mode transitions, enabling the circuit to prepare for low-power operation beforehand. This preliminary action allows the clock to be properly gated during sleep mode, reducing leakage currents while maintaining relatively simple circuit architecture.
Solution Approach 2:
The register serves as an intermediary that enables sophisticated clock control functionality without significantly increasing overall circuit complexity. By inserting this single register element, the circuit gains the ability to manage sleep mode transitions effectively, reducing leakage currents while adding minimal complexity.
Data Source
AI summary
An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.