Dynamic Clock Control for Parallel IC Self-Test Execution
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Solution Overview
Problem
In safety-critical integrated circuit applications, self-testing is limited by the need to minimize execution time and power consumption, where optimizing clock signals for speed increases execution time and reducing power consumption increases test time, creating a trade-off that affects availability and efficiency.
Innovation Solution
An integrated circuit device with self-test components executing tests in parallel, featuring a clock control component that dynamically modulates the clock signal by increasing its rate when self-testing ceases in one partition, utilizing spare power budget capacity to reduce overall execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the clock signal is optimized for maximum execution speed, then self-test execution time is minimized, but power consumption increases beyond the predefined power budget
Solution Approach 1:
The patent implements dynamic clock frequency adjustment during self-test execution. The clock control component monitors test completion status across partitions and dynamically modulates clock signal frequency - running at maximum frequency when all partitions are testing, and reducing frequency when some partitions complete early. This dynamic adaptation resolves the contradiction by matching clock speed to actual test progress rather than using a fixed high speed throughout.
Solution Approach 2:
The patent changes the clock signal parameter (frequency) based on test execution progress. The clock control component adjusts the frequency parameter dynamically - maintaining high frequency to minimize execution time when power budget allows, and reducing frequency when power consumption would exceed the budget. This parameter change strategy enables the system to navigate the trade-off between execution time and power consumption.
2Use of energy by moving object
If the clock signal speed is reduced to remain within power budget, then power consumption is controlled, but self-test execution time increases
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time monitoring of test completion status. When partitions complete their tests early, the clock frequency is reduced for remaining partitions, controlling power consumption. When all partitions are actively testing, maximum frequency is used to minimize execution time. This dynamic control resolves the contradiction by adapting power consumption to actual test needs.
Solution Approach 2:
The clock control component receives feedback from self-test components about test completion status and uses this feedback to adjust clock frequency. The feedback mechanism enables the system to respond to actual test progress - reducing frequency when power budget constraints are approached and increasing frequency when execution time can be reduced, thereby resolving the power-time trade-off.
3Loss of time
If self-tests are executed in parallel across multiple partitions, then overall execution time is reduced, but power consumption increases due to simultaneous operation of multiple components
Solution Approach 1:
The patent implements dynamic clock frequency modulation for parallel self-test execution across multiple partitions. The clock control component monitors which partitions are actively testing and adjusts clock frequency accordingly - maintaining high frequency for partitions still undergoing tests while reducing frequency for completed partitions. This dynamic approach enables parallel execution to reduce overall time while controlling power consumption by not maintaining high frequency unnecessarily.
Data Source
AI summary
An integrated circuit (IC) device, and method therefor, the IC device comprising a plurality of self-test components arranged to execute self-tests in parallel during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the plurality of self-test components at least during the self-test execution phase of the IC device. The at least one clock control component is further arranged to receive at least one indication that self-testing has ceased within at least a first self-test component, and dynamically modulate the at least one clock signal provided to at least one further self-test component for which self-testing has not ceased to increase a clock rate of the at least one clock signal upon receipt of an indication that self-test execution has ceased within the at least first self-test component.