Dynamic Clock Control for Neural Network Processors
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Solution Overview
Problem
Existing neural network technologies face challenges in achieving high computational and power efficiency, particularly in mobile devices, as they often rely on static methods like adaptive voltage scaling and dynamic voltage frequency scaling, which do not effectively adapt to dynamic changes in computational load, leading to inefficiencies in power usage and heat management.
Innovation Solution
Implementing a computationally driven dynamic clock control system that utilizes data sparsity information to adjust the neural network clock frequency through a closed-loop control mechanism, which generates a clock frequency control word based on current frame execution rates and a reference clock signal, allowing for real-time modulation of the operating frequency to match processing demands, thereby improving energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If static voltage scaling methods are used, then device complexity is reduced, but power efficiency and adaptability to dynamic computational load deteriorate
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by introducing a control mechanism that continuously monitors frame execution rates and dynamically modifies the neural network clock frequency. This transforms the static voltage scaling approach into a dynamic system that adapts to real-time computational demands, thereby improving power efficiency without excessive complexity increase
Solution Approach 2:
The patent employs feedback control by monitoring the actual frame execution rate and using this information to adjust the clock frequency. The control mechanism receives feedback about processing performance and automatically adjusts operational parameters to maintain optimal power efficiency, converting an open-loop static system into a closed-loop dynamic system
2Device complexity
If static voltage scaling methods are used, then device complexity is reduced, but adaptability to dynamic computational load deteriorates
Solution Approach 1:
The system transitions from static to dynamic operation by continuously adjusting clock frequency based on real-time frame execution rates. This dynamic adaptation allows the neural network processor to respond to varying computational demands, improving versatility without requiring overly complex control mechanisms
Solution Approach 2:
The patent changes the operational parameter being controlled from voltage (static scaling) to clock frequency (dynamic scaling). By modifying the frequency parameter in response to computational load variations, the system achieves better adaptability while maintaining relatively simple control logic
3Device complexity
If fixed clock frequency is used, then device complexity is reduced, but energy efficiency and TOPS/W deteriorate
Solution Approach 1:
The patent implements periodic monitoring and adjustment of clock frequency based on frame execution rates. By synchronizing clock adjustments with the periodic nature of neural network frame processing, the system achieves energy efficiency improvements while maintaining manageable control complexity through rhythm-based operation
Solution Approach 2:
The system dynamically changes the clock frequency parameter based on computational workload. During high-load periods, frequency increases to maintain performance; during low-load periods, frequency decreases to reduce power consumption, thereby improving overall energy efficiency without excessive control complexity
4Device complexity
If fixed clock frequency is used, then device complexity is reduced, but adaptability to varying computational loads deteriorates
Solution Approach 1:
The patent transforms the fixed clock frequency system into a dynamic one that automatically adjusts frequency based on computational load. This dynamic behavior enables the system to adapt to varying workloads while keeping control complexity manageable through automated feedback mechanisms
Data Source
AI summary
Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.